2025-02-03 07:51:54 +08:00
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#include "tl2cdr.h"
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2025-02-09 01:17:17 +08:00
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#include "sysDef.h"
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2025-02-12 15:58:50 +08:00
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#include "plic.h"
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2025-02-09 01:17:17 +08:00
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#if 0
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/*
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其他代码全部使用RV32E编译,仅此代码采用 RV32I 编译,故而可以使用x0, x16~x31寄存器
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为了方便,不再使用ABI中的别名,直接使用x0, x16~x31;x1~x15使用ABI中定义的别名
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*/
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#endif
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2025-03-03 10:59:07 +08:00
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#if !(defined(__riscv_i) || defined(__USE_RV32I_ABI))
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2025-02-10 14:38:49 +08:00
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#error "must be compiled in RV32I"
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#endif
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2025-02-03 07:51:54 +08:00
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.globl _prog_start
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.globl _rv32i_plic_handle
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.section .text.init, "ax", %progbits
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2025-02-12 15:58:50 +08:00
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_prog_start:
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2025-03-03 10:59:07 +08:00
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//a0 call_function no
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2025-02-12 15:58:50 +08:00
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li x16, SYS_INIT
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beqz a0, init_func //初始化系统,输入必要的地址信息,返回 中断程序 的地址
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li x16, SYS_SEND_DATA
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beq a0, x16, send_data_func
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li x16, SYS_SET_RECV_INFO
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beq a0, x16, set_recv_info_func
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li x16, SYS_SLAVE_WORK
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beq a0, x16, slave_work_func
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10: j 10b //死循环,输入错误的功能号
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ret //心理安慰,并不会返回
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2025-03-03 10:59:07 +08:00
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//---------------------------------------------------------
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//a1~a5
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2025-03-03 10:59:07 +08:00
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hlm_slave_work:
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li x18, 1
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i_rx0_txPair(x18)
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i_rx0_limitTime(x0)
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i_rx1_txPair(x0)
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i_rx1_limitTime(x0)
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1:
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i_hlm_read_intflag(x17)
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i_hlm_status(x16)
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2025-02-27 12:55:34 +08:00
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2025-03-03 10:59:07 +08:00
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andi x18, x17, HLM_INT_RX0_START
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ret
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//---------------------------------------------------------
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//初始化系统,输入必要的地址信息,返回中断程序的地址
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//a1, plic_claim的地址, 其实也可以不用传送
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init_func:
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2025-02-12 15:58:50 +08:00
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ret
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2025-02-03 07:51:54 +08:00
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2025-03-03 10:59:07 +08:00
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//---------------------------------------------------------
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2025-02-12 15:58:50 +08:00
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//主站启动发送数据
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//a1, 当前需要发送的数据的地址
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//a2, 当前数据发送的长度
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//a3, dummy
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//a4, dummy
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send_data_func:
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2025-03-03 10:59:07 +08:00
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#warning ..................................................
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2025-02-12 15:58:50 +08:00
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ret
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2025-03-03 10:59:07 +08:00
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//---------------------------------------------------------
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2025-02-12 15:58:50 +08:00
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//设置接收数据的地址,第一个接收数据的长度,往后都是数据
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//a1, 设置接收数据的缓冲区
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slave_work_func:
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1:
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2025-02-27 12:55:34 +08:00
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i_hlm_status(x18)
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andi x19, x18, HLM_RX0_VALID
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beqz x19, 1b
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2025-02-27 12:55:34 +08:00
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i_rx0_rxFifo(x20)
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srli x19, x20, 20
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addi x19, x19, 4
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i_tx1_txLen(x29)
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i_tx1_txFifo(x29)
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li x21, 4
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1:
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2025-02-27 12:55:34 +08:00
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i_hlm_status(x29)
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andi x18, x18, HLM_RX0_VALID
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beqz x18, 1b
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2025-02-27 12:55:34 +08:00
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i_rx0_rxFifo(x29)
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i_tx1_txFifo(x29)
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2025-02-12 15:58:50 +08:00
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addi x21, x21, 4
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bltu x21, x19, 1b
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ret
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2025-02-09 01:17:17 +08:00
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2025-03-03 10:59:07 +08:00
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//---------------------------------------------------------
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2025-02-09 01:17:17 +08:00
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set_recv_info_func:
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ret
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2025-03-03 10:59:07 +08:00
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//---------------------------------------------------------
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//中断程序,没有使用
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2025-02-03 07:51:54 +08:00
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.balign 32
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_rv32i_plic_handle:
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2025-02-09 01:17:17 +08:00
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mret
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2025-02-07 12:58:41 +08:00
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