eb001/Makefile

.PHONY: compile tb wave

compile:
	rm -rf ./generated/
	rm -rf ./rocket-chip/vsim/generated-src/
	mkdir -p ./generated/
	cd ./rocket-chip/ && rm -f rocketchip.jar
	cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.UserFPGAConfig
	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.v ./generated/UserFPGAConfig.v
	cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.UserFPGAConfig.behav_srams.v ./generated/behav_srams.v
# 	sbt "test:runMain test.testModule"

back:
	rm -f ./generated/back/*
	rm -f ./generated/cdr/*
	sbt "test:runMain test.testModule"
	cp ./src/main/verilog/backBoardMstTop.v ./generated/back/
	cp ./src/main/verilog/oser_rst.v ./generated/back/
	cp ./src/main/verilog/di16_top.v ./generated/back/
	cp ./src/main/verilog/do16_top.v ./generated/back/
	cp ./src/main/verilog/do16inv_top.v ./generated/back/
	cp ./src/main/verilog/qei_top.v ./generated/back/
	cp ./src/main/verilog/spi_top.v ./generated/back/
	cp ./src/main/verilog/defineParam.v ./generated/back/



ef: 
	sbt "test:runMain test.testModule"

VSimTop: 
	rm -rf ./tb/build/
	mkdir -p ./tb/build/
	verilator -Wno-fatal  \
	--timescale "1 ns / 1 ps" \
	-y ${PWD}/tb/ \
	-y ${PWD}/tb/vtb/ \
	--top-module SimTop \
	--trace-fst \
	--cc ./tb/behav_srams.v   \
	--cc ./tb/UserFPGAConfig.v \
	--cc ./tb/vtb/SimTop.v  \
	+define+RANDOMIZE_GARBAGE_ASSIGN \
	+define+RANDOMIZE_INVALID_ASSIGN \
	+define+RANDOMIZE_REG_INIT \
	+define+RANDOMIZE_MEM_INIT \
	+define+RANDOMIZE_DELAY=0 \
	+define+USE_POWER_PINS \
	--exe --build \
	${PWD}/tb/sim_main.cpp \
	-Mdir ./tb/build/ \
	-j 30


test:
	./tb/build/VSimTop -w -l -f ./tb/sw/build/test




sw:
	riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
	-I ./tb/sw/ -I ./tb/sw/src \
	-c ./tb/sw/src/mstStartup.S \
	-o ./tb/sw/build/mstStartup.o

	riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
	-I ./tb/sw/ -I ./tb/sw/src \
	-c ./tb/sw/src/mstMain.S \
	-o ./tb/sw/build/mstMain.o

	riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
	-T ./tb/sw/linker.lds \
	./tb/sw/build/mstStartup.o \
	./tb/sw/build/mstMain.o \
	-o ./tb/sw/build/mstTest.elf

	riscv64-unknown-elf-objcopy -O binary ./tb/sw/build/mstTest.elf  ./tb/sw/build/mstTest.bin

	riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/mstTest.elf > ./tb/sw/build/mstTest.dump

	riscv64-unknown-elf-objcopy -O verilog  ./tb/sw/build/mstTest.elf  ./tb/sw/build/mstTest.verilog
	sed -i 's/@800/@000/g' ./tb/sw/build/mstTest.verilog


	riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
	-I ./tb/sw/ -I ./tb/sw/src \
	-c ./tb/sw/src/slvStartup.S \
	-o ./tb/sw/build/slvStartup.o

	riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
	-I ./tb/sw/ -I ./tb/sw/src \
	-c ./tb/sw/src/slvMain.S \
	-o ./tb/sw/build/slvMain.o

	riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
	-T ./tb/sw/linker.lds \
	./tb/sw/build/slvStartup.o \
	./tb/sw/build/slvMain.o \
	-o ./tb/sw/build/slvTest.elf

	riscv64-unknown-elf-objcopy -O binary ./tb/sw/build/slvTest.elf  ./tb/sw/build/slvTest.bin

	riscv64-unknown-elf-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/slvTest.elf > ./tb/sw/build/slvTest.dump

	riscv64-unknown-elf-objcopy -O verilog  ./tb/sw/build/slvTest.elf  ./tb/sw/build/slvTest.verilog
	sed -i 's/@800/@000/g' ./tb/sw/build/slvTest.verilog


fst:
	gtkwave ./tb/build/wave.fst &



VSimBack: 
	rm -rf ./tb/build/
	mkdir -p ./tb/build/
	verilator -Wno-fatal  \
	--timescale "1 ns / 1 ps" \
	-y ${PWD}/tb/ \
	-y ${PWD}/generated/ \
	--top-module BackPlaneChainTest \
	--trace-fst \
	--cc ./generated/BackPlaneChainTest.v  \
	+define+RANDOMIZE_GARBAGE_ASSIGN \
	+define+RANDOMIZE_INVALID_ASSIGN \
	+define+RANDOMIZE_REG_INIT \
	+define+RANDOMIZE_MEM_INIT \
	+define+RANDOMIZE_DELAY=0 \
	--exe --build \
	${PWD}/tb/sim_backChain.cpp \
	-Mdir ./tb/build/ \
	-j 30



tb:
	iverilog -Wall \
	-o ./build/wave.iverilog  \
	-y ./tb  \
	-y ./generated/cdr/  \
	-I ./tb  \
	-I ./generated/cdr/  \
	-D RANDOMIZE_REG_INIT \
	./tb/backSys_tb.v 
	vvp  -N ./build/wave.iverilog -lxt2

vcd:
	gtkwave ./build/wave.vcd &