78 lines
1.8 KiB
Scala
78 lines
1.8 KiB
Scala
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package BACK
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import chisel3._
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import chisel3.util._
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class SimCDR extends Module with RequireAsyncReset{
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val io = IO(new Bundle{
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val data = Input( UInt(8.W) )
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val multiCLK = Input(Vec(16, Bool()))
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val flush = Input(Bool())
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val isSuccess = Output(Bool())
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val isFailed = Output(Bool())
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})
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val cdrIn = Module(new MPCDRIn)
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val cdrOut = Module(new CDROut)
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val record = Module( new Queue(UInt(8.W), 256) )
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val dataCnt = RegInit(0.U(12.W))
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val payloadLen = RegInit(("hFFF".U)(12.W))
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when( cdrOut.io.axis.fire & dataCnt === 0.U ){
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payloadLen := Cat( io.data, 0.U(4.W) )
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} .elsewhen( cdrOut.io.axis.fire & dataCnt === 1.U ){
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payloadLen := Cat( payloadLen(11,4), io.data(7,4) ) + 4.U + 4.U
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}
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when( cdrOut.io.axis.fire ){
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when( dataCnt >= payloadLen - 1.U ){
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dataCnt := 0.U
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} .otherwise{
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dataCnt := dataCnt + 1.U
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}
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}
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cdrOut.io.flush := io.flush
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cdrIn.clock := io.multiCLK(0).asClock
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cdrIn.io.flush := io.flush
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cdrIn.multiCLK := io.multiCLK
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cdrIn.io.serDat := cdrOut.io.serDat
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assert( ~(record.io.enq.valid & ~record.io.enq.ready), "Assert Failed, Warning, fifo overflow!\n" )
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assert( ~(~record.io.deq.valid & record.io.deq.ready), "Assert Failed, Warning, fifo underflow!\n" )
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val isTxEnd = cdrOut.io.axis.fire & cdrOut.io.axis.bits.tlast
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cdrOut.io.axis.valid := ~io.flush & ShiftRegisters( ~isTxEnd, 16 ).reduce(_&_)
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cdrOut.io.axis.bits.tdata := io.data
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cdrOut.io.axis.bits.tuser := false.B
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cdrOut.io.axis.bits.tlast := dataCnt === (payloadLen - 1.U)
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record.io.enq.valid := cdrOut.io.axis.fire
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record.io.enq.bits := io.data
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record.io.deq.ready := cdrIn.io.axis.fire
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cdrIn.io.axis.ready := true.B
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io.isFailed := cdrIn.io.axis.fire & (record.io.deq.bits =/= cdrIn.io.axis.bits.tdata)
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io.isSuccess := cdrIn.io.axis.fire & cdrIn.io.axis.bits.tlast
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}
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