package BACK

import chisel3._
import chisel3.util._



class SimCDR extends Module with RequireAsyncReset{
  val io = IO(new Bundle{
    val data = Input( UInt(8.W) )

    val multiCLK = Input(Vec(16, Bool()))

    val flush = Input(Bool())

    val isSuccess = Output(Bool())
    val isFailed = Output(Bool())
  })




  val cdrIn = Module(new MPCDRIn)
  val cdrOut = Module(new CDROut)
  val record = Module( new Queue(UInt(8.W), 256) )

  val dataCnt = RegInit(0.U(12.W))
  val payloadLen = RegInit(("hFFF".U)(12.W))

   
  when( cdrOut.io.axis.fire & dataCnt === 0.U ){
    payloadLen := Cat( io.data, 0.U(4.W) )
  } .elsewhen( cdrOut.io.axis.fire & dataCnt === 1.U ){
    payloadLen := Cat( payloadLen(11,4), io.data(7,4) ) + 4.U + 4.U
  }

  when( cdrOut.io.axis.fire ){
    when( dataCnt >= payloadLen - 1.U ){
      dataCnt := 0.U
    } .otherwise{
      dataCnt := dataCnt + 1.U
    }
  }


  cdrOut.io.flush := io.flush

  cdrIn.clock := io.multiCLK(0).asClock
  cdrIn.io.flush := io.flush
  cdrIn.multiCLK := io.multiCLK

  cdrIn.io.serDat := cdrOut.io.serDat

  assert( ~(record.io.enq.valid  & ~record.io.enq.ready), "Assert Failed, Warning, fifo overflow!\n" )
  assert( ~(~record.io.deq.valid & record.io.deq.ready),  "Assert Failed, Warning, fifo underflow!\n" )

  val isTxEnd = cdrOut.io.axis.fire & cdrOut.io.axis.bits.tlast

  cdrOut.io.axis.valid := ~io.flush & ShiftRegisters( ~isTxEnd, 16 ).reduce(_&_)
  cdrOut.io.axis.bits.tdata  := io.data
  cdrOut.io.axis.bits.tuser  := false.B
  cdrOut.io.axis.bits.tlast  := dataCnt === (payloadLen - 1.U)



  record.io.enq.valid := cdrOut.io.axis.fire
  record.io.enq.bits  := io.data

  record.io.deq.ready := cdrIn.io.axis.fire
  cdrIn.io.axis.ready := true.B

  io.isFailed  := cdrIn.io.axis.fire & (record.io.deq.bits =/= cdrIn.io.axis.bits.tdata)
  io.isSuccess := cdrIn.io.axis.fire & cdrIn.io.axis.bits.tlast

}