65 lines
1.5 KiB
Scala
65 lines
1.5 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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import chisel3.experimental.dataview._
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class ShinTopIO extends TopBase_IO_Bundle{
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val multiCLK = Input(Vec(16, Bool()))
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val multiCLKDiv4 = Input(Vec(4, Bool()))
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}
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class ShinTop extends Module with RequireAsyncReset{
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val io: ShinTopIO = IO(new ShinTopIO)
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val mstSlvSwitch = Module(new MstSlvSwitch)
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{
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val downCDRInSampleA = Module(new CDRInMultiSample)
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val upCDRInSampleA = Module(new CDRInMultiSample)
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downCDRInSampleA.multiCLK := io.multiCLK
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upCDRInSampleA.multiCLK := io.multiCLK
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downCDRInSampleA.io <> mstSlvSwitch.io.downCDRSampleIn(0)
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upCDRInSampleA.io <> mstSlvSwitch.io.upCDRSampleIn(0)
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}
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{
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val downCDRInSampleB = Module(new CDRInMultiSample)
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val upCDRInSampleB = Module(new CDRInMultiSample)
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downCDRInSampleB.multiCLK := io.multiCLK
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upCDRInSampleB.multiCLK := io.multiCLK
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downCDRInSampleB.io <> mstSlvSwitch.io.downCDRSampleIn(1)
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upCDRInSampleB.io <> mstSlvSwitch.io.upCDRSampleIn(1)
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}
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{
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val downCDRInSampleC = Module(new CDRInMultiSample)
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val upCDRInSampleC = Module(new CDRInMultiSample)
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downCDRInSampleC.multiCLK := io.multiCLK
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upCDRInSampleC.multiCLK := io.multiCLK
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downCDRInSampleC.io <> mstSlvSwitch.io.downCDRSampleIn(2)
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upCDRInSampleC.io <> mstSlvSwitch.io.upCDRSampleIn(2)
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}
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io.viewAsSupertype(new TopBase_IO_Bundle) <> mstSlvSwitch.io.viewAsSupertype(new TopBase_IO_Bundle)
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}
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