305 lines
9.8 KiB
Scala
305 lines
9.8 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class CRC_ERR_Bundle extends Bundle{
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val crc_err = Bool()
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val crc_err_count = UInt(8.W)
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val cdr_err = Bool()
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}
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class Lvds_Bus_MasterIO extends Bundle{
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val rst_n = Input(Bool())
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val reset_calib = Input(Bool())
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val oser_pclk = Input(Bool())
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val oser_fclk = Input(Bool())
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val ides_pclk = Input(Bool())
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val ides_fclk = Input(Bool())
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val lvds_down_dout = Output(Bool())
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val lvds_up_din = Input(Bool())
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val frame_info_update_en = Input(Bool())
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val slave_type_num = Input(UInt(8.W))
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val slave_data_length = Input(UInt(8.W))
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val slave_link_num_valid = Output(Bool())
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val slave_link_num = Output(UInt(7.W))
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val tx_start = Input(Bool())
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val tx_data_in = Input(UInt(8.W))
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val tx_data_ready = Output(Bool())
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val downstream_busy = Output(Bool())
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val rx_data_out = Output(UInt(8.W))
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val rx_data_valid = Output(Bool())
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val upstream_crc_valid = Output(Bool())
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val upstream_crc_err = Output(Bool())
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val upstream_crc_err_count = Output(UInt(8.W))
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val upstream_cdr_err = Output(Bool())
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val closed_loop_err = Output(Bool())
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val link_err_location = Output(UInt(7.W))
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val test_downstream_tx_en = Output(Bool())
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val test_downstream_tx_8b_data = Output(UInt(8.W))
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val test_downstream_tx_10b_data = Output(UInt(10.W))
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val test_upstream_rx_busy = Output(Bool())
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val test_upstream_rx_10b_data = Output(UInt(10.W))
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val test_upstream_rx_8b_data = Output(UInt(8.W))
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}
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class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
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val io: Lvds_Bus_MasterIO = IO(new Lvds_Bus_MasterIO)
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setInline("lvds_Bus_Master.v",
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"""
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| module Lvds_Bus_Master(
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| input rst_n,
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| input reset_calib,
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| input oser_pclk,
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| input oser_fclk,
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| input ides_pclk,
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| input ides_fclk,
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| output lvds_down_dout,
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| input lvds_up_din,
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| input frame_info_update_en,
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| input [7:0] slave_type_num,
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| input [7:0] slave_data_length,
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| output slave_link_num_valid,
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| output [6:0] slave_link_num,
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| input tx_start,
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| input [7:0] tx_data_in,
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| output tx_data_ready,
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| output downstream_busy,
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| output [7:0] rx_data_out,
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| output rx_data_valid,
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| output upstream_crc_valid,
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| output upstream_crc_err,
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| output [7:0] upstream_crc_err_count,
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| output upstream_cdr_err,
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| output closed_loop_err,
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| output [6:0] link_err_location,
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| output test_downstream_tx_en,
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| output [7:0] test_downstream_tx_8b_data,
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| output [9:0] test_downstream_tx_10b_data,
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| output test_upstream_rx_busy,
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| output [9:0] test_upstream_rx_10b_data,
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| output [7:0] test_upstream_rx_8b_data
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| );
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| lvds_bus_master_top i_lvds_bus_master(
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| .rst_n(rst_n), //input
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| .reset_calib(reset_calib), //input
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| .oser_pclk(oser_pclk), //input
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| .oser_fclk(oser_fclk), //input
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| .ides_pclk(ides_pclk), //input
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| .ides_fclk(ides_fclk), //input
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| .lvds_down_dout(lvds_down_dout), //output
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| .lvds_up_din(lvds_up_din), //input
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| .frame_info_update_en(frame_info_update_en), //input
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| .slave_type_num(slave_type_num), //input [7:0]
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| .slave_data_length(slave_data_length), //input [7:0]
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| .slave_link_num_valid(slave_link_num_valid), //output
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| .slave_link_num(slave_link_num), //output [6:0]
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| .tx_start(tx_start), //input
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| .tx_data_in(tx_data_in), //input [7:0]
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| .tx_data_ready(tx_data_ready), //output
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| .downstream_busy(downstream_busy), //output
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| .rx_data_out(rx_data_out), //output [7:0]
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| .rx_data_valid(rx_data_valid), //output
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| .upstream_crc_valid(upstream_crc_valid), //output
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| .upstream_crc_err(upstream_crc_err), //output
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| .upstream_crc_err_count(upstream_crc_err_count), //output [7:0]
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| .upstream_cdr_err(upstream_cdr_err), //output
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| .closed_loop_err(closed_loop_err), //output
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| .link_err_location(link_err_location), //output [6:0]
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| .test_downstream_tx_en(test_downstream_tx_en), //output
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| .test_downstream_tx_8b_data(test_downstream_tx_8b_data), //output [7:0]
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| .test_downstream_tx_10b_data(test_downstream_tx_10b_data), //output [9:0]
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| .test_upstream_rx_busy(test_upstream_rx_busy), //output
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| .test_upstream_rx_10b_data(test_upstream_rx_10b_data), //output [9:0]
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| .test_upstream_rx_8b_data(test_upstream_rx_8b_data) //output [7:0]
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| );
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|endmodule
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""".stripMargin)
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}
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class Lvds_Bus_SlaveIO extends Bundle{
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val rst_n = Input(Bool())
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val reset_calib = Input(Bool())
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val oser_pclk = Input(Bool())
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val oser_fclk = Input(Bool())
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val ides_pclk = Input(Bool())
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val ides_fclk = Input(Bool())
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val lvds_down_din = Input(Bool())
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val lvds_down_dout = Output(Bool())
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val lvds_up_din = Input(Bool())
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val lvds_up_dout = Output(Bool())
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val downstream_rx_data_valid = Output(Bool())
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val downstream_rx_data_out = Output(UInt(8.W))
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val downstream_rx_crc_valid = Output(Bool())
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val downstream_rx_crc_err = Output(Bool())
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val downstream_rx_crc_err_counter = Output(UInt(8.W))
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val downstream_rx_cdr_err = Output(Bool())
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val downstream_sync = Output(Bool())
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val upstream_tx_data_ready = Output(Bool())
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val upstream_tx_data_in = Input(UInt(8.W))
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val upstream_rx_crc_valid = Output(Bool())
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val upstream_rx_crc_err = Output(Bool())
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val upstream_rx_crc_err_counter = Output(UInt(8.W))
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val upstream_rx_cdr_err = Output(Bool())
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val local_slave_id = Output(UInt(7.W))
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val test_downstream_rx_10b_data = Output(UInt(10.W))
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val test_downstream_rx_8b_data = Output(UInt(8.W))
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val test_downstream_rx_state_machine = Output(UInt(4.W))
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val test_downstream_tx_en = Output(Bool())
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val test_downstream_tx_8b_data = Output(UInt(8.W))
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val test_downstream_tx_10b_data = Output(UInt(10.W))
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val test_upstream_rx_10b_data = Output(UInt(10.W))
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val test_upstream_rx_8b_data = Output(UInt(8.W))
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val test_upstream_rx_state_machine = Output(UInt(4.W))
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val test_upstream_tx_en = Output(Bool())
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val test_upstream_tx_8b_data = Output(UInt(8.W))
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val test_upstream_tx_10b_data = Output(UInt(10.W))
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}
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class Lvds_Bus_Slave extends BlackBox with HasBlackBoxInline {
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val io: Lvds_Bus_SlaveIO = IO(new Lvds_Bus_SlaveIO)
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setInline("Lvds_Bus_Slave.v",
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"""
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module Lvds_Bus_Slave(
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| input rst_n,
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| input reset_calib,
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| input oser_pclk,
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| input oser_fclk,
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| input ides_pclk,
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| input ides_fclk,
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| input lvds_down_din,
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| output lvds_down_dout,
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| input lvds_up_din,
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| output lvds_up_dout,
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| output downstream_rx_data_valid,
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| output downstream_rx_unicast_pkg_valid,
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| output [7:0] downstream_rx_data_out,
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| output downstream_rx_crc_valid,
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| output downstream_rx_crc_err,
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| output [7:0] downstream_rx_crc_err_counter,
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| output downstream_rx_cdr_err,
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| output downstream_sync,
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| output upstream_tx_data_ready,
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| output upstream_tx_unicast_pkg_ready,
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| input [7:0] upstream_tx_data_in,
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| output upstream_rx_crc_valid,
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| output upstream_rx_crc_err,
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| output [7:0] upstream_rx_crc_err_counter,
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| output upstream_rx_cdr_err,
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| output [6:0] local_slave_id,
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| output [9:0] test_downstream_rx_10b_data,
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| output [7:0] test_downstream_rx_8b_data,
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| output [3:0] test_downstream_rx_state_machine,
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| output test_downstream_tx_en,
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| output [7:0] test_downstream_tx_8b_data,
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| output [9:0] test_downstream_tx_10b_data,
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| output [9:0] test_upstream_rx_10b_data,
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| output [7:0] test_upstream_rx_8b_data,
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| output [3:0] test_upstream_rx_state_machine,
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| output test_upstream_tx_en,
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| output [7:0] test_upstream_tx_8b_data,
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| output [9:0] test_upstream_tx_10b_data
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|);
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| lvds_bus_slave_top i_lvds_bus_slave(
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| .rst_n(rst_n),
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| .reset_calib(reset_calib),
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| .oser_pclk(oser_pclk),
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| .oser_fclk(oser_fclk),
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| .ides_pclk(ides_pclk),
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| .ides_fclk(ides_fclk),
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| .lvds_down_din(lvds_down_din),
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| .lvds_down_dout(lvds_down_dout),
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| .lvds_up_din(lvds_up_din),
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| .lvds_up_dout(lvds_up_dout),
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| .downstream_rx_data_valid(downstream_rx_data_valid),
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| .downstream_rx_unicast_pkg_valid(downstream_rx_unicast_pkg_valid),
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| .downstream_rx_data_out(downstream_rx_data_out),
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| .downstream_rx_crc_valid(downstream_rx_crc_valid),
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| .downstream_rx_crc_err(downstream_rx_crc_err),
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| .downstream_rx_crc_err_counter(downstream_rx_crc_err_counter),
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| .downstream_rx_cdr_err(downstream_rx_cdr_err),
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| .downstream_sync(downstream_sync),
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| .upstream_tx_data_ready(upstream_tx_data_ready),
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| .upstream_tx_unicast_pkg_ready(upstream_tx_unicast_pkg_ready),
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| .upstream_tx_data_in(upstream_tx_data_in),
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| .upstream_rx_crc_valid(upstream_rx_crc_valid),
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| .upstream_rx_crc_err(upstream_rx_crc_err),
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| .upstream_rx_crc_err_counter(upstream_rx_crc_err_counter),
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| .upstream_rx_cdr_err(upstream_rx_cdr_err),
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| .local_slave_id(local_slave_id), //output[6:0]
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| .test_downstream_rx_10b_data(test_downstream_rx_10b_data), //output[9:0]
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| .test_downstream_rx_8b_data(test_downstream_rx_8b_data), //output[7:0]
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| .test_downstream_rx_state_machine(test_downstream_rx_state_machine), //output[3:0]
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| .test_downstream_tx_en(test_downstream_tx_en), //output
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| .test_downstream_tx_8b_data(test_downstream_tx_8b_data), //output[7:0]
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| .test_downstream_tx_10b_data(test_downstream_tx_10b_data), //output[9:0]
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| .test_upstream_rx_10b_data(test_upstream_rx_10b_data), //output[9:0]
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| .test_upstream_rx_8b_data(test_upstream_rx_8b_data), //output[7:0]
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| .test_upstream_rx_state_machine(test_upstream_rx_state_machine), //output[3:0]
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| .test_upstream_tx_en(test_upstream_tx_en), //output
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| .test_upstream_tx_8b_data(test_upstream_tx_8b_data), //output[7:0]
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| .test_upstream_tx_10b_data(test_upstream_tx_10b_data) //output[9:0]
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| );
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|endmodule
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""".stripMargin)
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}
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//Test Signal//
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