139 lines
3.6 KiB
Scala
139 lines
3.6 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>
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val inPin = Wire(UInt(16.W))
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val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) ))
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val flitTrigger = Wire(Vec(9, Bool()))
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val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 1.U(8.W) ) }
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val digitalIn = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) }
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flitTrigger(0) := ~RegNext(flitTrigger(0))
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flitTrigger(1) := flitCnt(1) === 15.U
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when( ~RegNext(usTrigger) & usTrigger ){
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flitCnt(1) := flitCnt(1) + 1.U
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}
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flitTrigger(2) := flitCnt(2)
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when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){
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flitCnt(2) := ~flitCnt(2)
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}
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flitTrigger(3) := flitCnt(3)
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when( ~RegNext(flitTrigger(2)) & flitTrigger(2) ){
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flitCnt(3) := ~flitCnt(3)
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}
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flitTrigger(4) := flitCnt(4)
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when( ~RegNext(flitTrigger(3)) & flitTrigger(3) ){
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flitCnt(4) := ~flitCnt(4)
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}
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flitTrigger(5) := flitCnt(5)
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when( ~RegNext(flitTrigger(4)) & flitTrigger(4) ){
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flitCnt(5) := ~flitCnt(5)
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}
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flitTrigger(6) := flitCnt(6)
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when( ~RegNext(flitTrigger(5)) & flitTrigger(5) ){
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flitCnt(6) := ~flitCnt(6)
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}
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flitTrigger(7) := flitCnt(7)
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when( ~RegNext(flitTrigger(6)) & flitTrigger(6) ){
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flitCnt(7) := ~flitCnt(7)
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}
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flitTrigger(8) := flitCnt(8)
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when( ~RegNext(flitTrigger(7)) & flitTrigger(7) ){
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flitCnt(8) := ~flitCnt(8)
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}
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for( i <- 0 until 8 ) {
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for( j <- 0 until 2 ) {
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val flitter = RegInit(VecInit( Seq.fill(16){false.B}))
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val flitHi = RegInit(0.U((log2Ceil(16)).W))
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val shiftIn = RegNext( inPin(i+8*j) )
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val sample =
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Mux( digitalFilter(j) === 1.U, ~RegNext(flitTrigger(1)) & flitTrigger(1),
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Mux(digitalFilter(j) === 2.U, ~RegNext(flitTrigger(2)) & flitTrigger(2),
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Mux(digitalFilter(j) === 3.U, ~RegNext(flitTrigger(3)) & flitTrigger(3),
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Mux(digitalFilter(j) === 4.U, ~RegNext(flitTrigger(4)) & flitTrigger(4),
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Mux(digitalFilter(j) === 5.U, ~RegNext(flitTrigger(5)) & flitTrigger(5),
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Mux(digitalFilter(j) === 6.U, ~RegNext(flitTrigger(6)) & flitTrigger(6),
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Mux(digitalFilter(j) === 7.U, ~RegNext(flitTrigger(7)) & flitTrigger(7),
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Mux(digitalFilter(j) === 8.U, ~RegNext(flitTrigger(8)) & flitTrigger(8), true.B
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))))))))
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when( sample ){
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flitter(0) := shiftIn
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(1 until 16).map{ k =>
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flitter(k) := flitter(k-1)
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}
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when( ~flitter(15) & flitter(0) ){
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flitHi := flitHi + 1.U
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} .elsewhen( flitter(15) & ~flitter(0) ){
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flitHi := flitHi - 1.U
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}
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when( flitHi === 12.U ){
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digitalIn(j)(i) := true.B
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} .elsewhen( flitHi === 3.U ){
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digitalIn(j)(i) := false.B
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}
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// val fliterCnt = WireDefault( VecInit( (1 until 16).map{ k => flitter(k) }) )
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// assert( flitHi <= 15.U )
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// assert( fliterCnt.count( (k:Bool) => k === true.B ) === flitHi )
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}
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}
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}
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}
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class DIn16 extends BackBoardSlvLocal
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with BackBoardSlvStatusPR
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with BackBoardSlvIn16{
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val in = IO(Input(UInt(16.W)))
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inPin := in
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when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
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digitalFilter(0) := downRegTemp(4)
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digitalFilter(1) := downRegTemp(5)
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}
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val digitalInSync = for( i <- 0 until 2 ) yield { RegEnable( Cat( digitalIn(i).reverse ), isUpdate ) }
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when( statusPage === 0.U ){
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upReg(2) := digitalInSync(0)
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upReg(3) := digitalInSync(1)
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upReg(4) := digitalFilter(0)
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upReg(5) := digitalFilter(1)
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}
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}
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