152 lines
5.9 KiB
Scala
152 lines
5.9 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class SlaveRecParserIO extends Module{
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val rec = Flipped( Decoupled(new AXIS_Bundle(8)) )
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val data = Decoupled(UInt(8.W))
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val stateNext = Output(UInt(4.W))
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val stateCurr = Output(UInt(4.W))
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val frameReq = Valid( new Bundle{
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val frameLenAim = Output(UInt(12.W)) //帧长度目标
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val frameStyle = Output(UInt(2.W)) //包类型
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} )
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val subMsgReq = Valid( new Bundle{
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val subMsg_devIndex = Output(UInt(14.W)) // 子报文中设备索引
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val subMsg_style = Output(UInt(2.W)) // 子报文类型
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val subMsg_address = Output(UInt(16.W)) //子报文地址
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val subMsg_operator = Output(UInt(4.W)) //子报文命令类型
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val subMsg_length = Output(UInt(12.W)) //子报文负载长度
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val subMsg_workCnt = Output(UInt(16.W)) //子报文工作计数
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)
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}
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class SlaveRecParser extends Module{
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val io: SlaveRecParserIO = IO(new SlaveRecParserIO)
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val FRAME_STYLE_COMMON = 0.U
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val FRAME_STYLE_PROBE = 1.U
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val STATE_IDLE = 0.U //空闲
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val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
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val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
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val STATE_PAYLOAD_ADDR = 3.U //子报文地址
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val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度
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val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数
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val STATE_PAYLOAD_DATA = 6.U //子报文数据
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val STATE_CRC = 7.U //CRC校验
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val STATE_ERROR = 8.U //
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val STATE_WAIT = 9.U
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val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext
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val stateCurr = RegNext(stateNext, STATE_IDLE(4.W)); io.stateCurr := stateCurr
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val lengthCnt = Reg(UInt(11.W)) //动态计数器
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val frameLenCnt = Reg(UInt(12.W)) //帧长度计数
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val isCrcPass: Bool
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val isTxEnd: Bool
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val isShortRx: Bool //接收长度小于预期
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val frameLenAim = Reg(UInt(12.W)); io.frameLenAim := frameLenAim //帧长度目标
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val frameStyle = Reg(UInt(2.W)); io.frameStyle := frameStyle //包类型
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val subMsg_devIndex = Reg(UInt(14.W)); io.subMsg_devIndex := subMsg_devIndex // 子报文中设备索引
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val subMsg_style = Reg(UInt(2.W)); io.subMsg_style := subMsg_style // 子报文类型
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val subMsg_address = Reg(UInt(16.W)); io.subMsg_address := subMsg_address //子报文地址
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val subMsg_operator = Reg(UInt(4.W)); io.subMsg_operator := subMsg_operator //子报文命令类型
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val subMsg_length = Reg(UInt(12.W)); io.subMsg_length := subMsg_length //子报文负载长度
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val subMsg_workCnt = Reg(UInt(16.W)); io.subMsg_workCnt := subMsg_workCnt //子报文工作计数
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when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){
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frameLenAim := io.rec.bits.tdata << 4
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} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 1.U ){
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frameLenAim := frameLenAim | io.rec.bits.tdata(7,4)
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frameStyle := io.rec.bits.tdata(1,0)
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}
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when( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 0.U ){
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subMsg_devIndex := io.rec.bits.tdata << 6
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} .elsewhen( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 1.U ){
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subMsg_devIndex := subMsg_devIndex | io.rec.bits.tdata(7,2)
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subMsg_style := io.rec.bits.tdata(1,0)
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}
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when( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 0.U ){
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subMsg_address := io.rec.bits.tdata << 8
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} .elsewhen( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 1.U ){
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subMsg_address := subMsg_address | io.rec.bits.tdata
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}
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when( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 0.U ){
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subMsg_operator := io.rec.bits.tdata(7,4)
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subMsg_length := io.rec.bits.tdata(3,0) << 8
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} .elsewhen( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 1.U ){
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subMsg_length := subMsg_length | io.rec.bits.tdata(7,0)
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}
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when( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 0.U ){
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subMsg_workCnt := io.rec.bits.tdata(7,0) << 8
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} .elsewhen( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 1.U ){
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subMsg_workCnt := subMsg_workCnt | io.rec.bits.tdata(7,0)
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}
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stateNext :=
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Mux1H(Seq(
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//必须使用上升沿触发，以避免前一帧长度超过预期
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( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.axis.valid, STATE_HEADER, STATE_IDLE ),
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( stateCurr === STATE_HEADER ) -> Mux( isShortRx, STATE_ERROR,
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Mux( lengthCnt === 0, STATE_HEADER,
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MuxCase( STATE_ERROR, Array(
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( io.rec.bits(1,0) === FRAME_STYLE_COMMON ) -> STATE_PAYLOAD_INDEX_STYLE,
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( io.rec.bits(1,0) === FRAME_STYLE_PROBE ) -> STATE_CRC,
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))
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)
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),
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( stateCurr === STATE_PAYLOAD_INDEX_STYLE ) -> Mux( isShortRx, STATE_ERROR,
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Mux( lengthCnt === 0, STATE_PAYLOAD_INDEX_STYLE, STATE_PAYLOAD_ADDR )
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),
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( stateCurr === STATE_PAYLOAD_ADDR ) -> Mux( isShortRx, STATE_ERROR,
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Mux( lengthCnt === 0, STATE_PAYLOAD_ADDR, STATE_PAYLOAD_OP_LENGTH )
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),
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( stateCurr === STATE_PAYLOAD_OP_LENGTH ) -> Mux( isShortRx, STATE_ERROR,
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Mux( lengthCnt === 0, STATE_PAYLOAD_OP_LENGTH, STATE_PAYLOAD_WORKCNT )
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),
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( stateCurr === STATE_PAYLOAD_WORKCNT ) -> Mux( isShortRx, STATE_ERROR,
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Mux( lengthCnt === 0.U, STATE_PAYLOAD_WORKCNT, STATE_PAYLOAD_DATA )
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),
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( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( isShortRx, STATE_ERROR,
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Mux( lengthCnt === ( subMsgLen - 1.U),
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Mux( frameLenCnt === frameLenAim, STATE_CRC, STATE_PAYLOAD_INDEX_STYLE
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), STATE_PAYLOAD_DATA )
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),
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( stateCurr === STATE_CRC ) -> Mux( isShortRx, STATE_ERROR,
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Mux( lengthCnt === (4 - 1).U, Mux( isCrcPass, STATE_IDLE, STATE_ERROR), STATE_CRC )
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),
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( stateCurr === STATE_ERROR ) -> Mux( isTxEnd, STATE_IDLE, STATE_ERROR ),
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( stateCurr === STATE_WAIT ) ->
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))
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}
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