161 lines
5.9 KiB
Scala
161 lines
5.9 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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trait BackBoardSlvQei{ this: BackBoardSlvLocal =>
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val phaseA = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val phaseB = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val phaseZ = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val counter = for( i <- 0 until 2 ) yield { Reg(UInt(33.W)) }
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val encordNxt = for( i <- 0 until 2 ) yield { Cat( phaseB(i), phaseA(i) ) }
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val encordCur = for( i <- 0 until 2 ) yield { RegNext(encordNxt(i)) }
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val isEnable = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val isSign = for( i <- 0 until 2 ) yield { Reg(Bool()) }
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val isSetVal = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val initVal = for( i <- 0 until 2 ) yield { Reg(UInt(32.W)) }
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val mode = for( i <- 0 until 2 ) yield { Reg(UInt(2.W)) }
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val invDirect = for( i <- 0 until 2 ) yield { Reg(Bool()) }
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val is2Phase = for( i <- 0 until 2 ) yield { Reg(Bool()) }
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val isZPhaseEnable = for( i <- 0 until 2 ) yield { Reg(Bool()) }
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val isSetValPos = for( i <- 0 until 2 ) yield { ~RegNext( isSetVal(i), false.B ) & isSetVal(i) }
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val isSetValNeg = for( i <- 0 until 2 ) yield { RegNext( isSetVal(i), false.B ) & ~isSetVal(i) }
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val isAdvA = for( i <- 0 until 2 ) yield {
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( encordCur(i) === "b00".U & encordNxt(i) === "b01".U & mode(i).extract(1)) |
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( encordCur(i) === "b01".U & encordNxt(i) === "b11".U & mode(i) =/= "b00".U ) |
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( encordCur(i) === "b11".U & encordNxt(i) === "b10".U & mode(i).extract(1)) |
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( encordCur(i) === "b10".U & encordNxt(i) === "b00".U )
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}
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val isAdvB = for( i <- 0 until 2 ) yield {
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( encordNxt(i) === "b00".U & encordCur(i) === "b01".U ) |
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( encordNxt(i) === "b01".U & encordCur(i) === "b11".U & mode(i).extract(1)) |
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( encordNxt(i) === "b11".U & encordCur(i) === "b10".U & mode(i) =/= "b00".U ) |
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( encordNxt(i) === "b10".U & encordCur(i) === "b00".U & mode(i).extract(1))
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}
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val isMiss = for( i <- 0 until 2 ) yield { encordCur(i) === ~encordNxt(i) }
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// val isKeep = for( i <- 0 until 2 ) yield { encordCur(i) === encordNxt(i) }
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val isOverflow = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val isCounter32Flip = for( i <- 0 until 2 ) yield { RegNext( counter(i).extract(32)) =/= counter(i).extract(32) }
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val isCounter31Flip = for( i <- 0 until 2 ) yield { (RegNext( counter(i).extract(31)) =/= counter(i).extract(31)) & (RegNext( counter(i).extract(32)) === counter(i).extract(32)) }
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for( i <- 0 until 2 ){
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isOverflow(i) := false.B
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when( isZPhaseEnable(i) & phaseZ(i) ){ //Z Phase reset
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counter(i) := initVal(i)
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} .elsewhen( isSetValPos(i) ){
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counter(i) := initVal(i)
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} .elsewhen( isSetValNeg(i) ){
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counter(i) := 0.U
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} .otherwise{
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when(isEnable(i)){
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when(~is2Phase(i)){ //A Phase only
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when( RegNext( phaseA(i) ) & ~phaseA(i) ){
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counter(i) := counter(i) + 1.U
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}
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isOverflow(i) := isSetVal(i) & isCounter32Flip(i)
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} .otherwise{ //AB Phase
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when( invDirect(i) ) {
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when(isAdvA(i)){
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counter(i) := counter(i) - 1.U
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} .elsewhen(isAdvB(i)){
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counter(i) := counter(i) + 1.U
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}
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} .otherwise{ //~invDirect(i)
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when(isAdvA(i)){
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counter(i) := counter(i) + 1.U
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} .elsewhen(isAdvB(i)){
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counter(i) := counter(i) - 1.U
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}
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}
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isOverflow(i) :=
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Mux( isSign(i), isSetVal(i) & isCounter31Flip(i), isSetVal(i) & isCounter32Flip(i) )
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}
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} .otherwise{ //~isEnable
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counter(i) := initVal(i)
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}
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}
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}
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}
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class Qei extends BackBoardSlvLocal with BackBoardSlvStatusPR with BackBoardSlvQei{
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val phaseAIO = for( i <- 0 until 2 ) yield { IO(Input(Bool())) }
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val phaseBIO = for( i <- 0 until 2 ) yield { IO(Input(Bool())) }
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val phaseZIO = for( i <- 0 until 2 ) yield { IO(Input(Bool())) }
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for( i <- 0 until 2 ){
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phaseA(i) := RegNext(phaseAIO(i))
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phaseB(i) := RegNext(phaseBIO(i))
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phaseZ(i) := RegNext(phaseZIO(i))
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}
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for( i <- 0 until 2 ){
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when(isOverflow(i)){
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isEnable(i) := false.B
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} .elsewhen( (isCrcPass & downRegTemp(0)(3,0) === 0.U) & ~downRegTemp(2+i).extract(0) ){
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isEnable(i) := false.B
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} .elsewhen( (isCrcPass & downRegTemp(0)(3,0) === 0.U) & downRegTemp(2+i).extract(0) ){
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isEnable(i) := true.B
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}
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when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
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isZPhaseEnable(i) := downRegTemp(2+(2*i)).extract(1)
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is2Phase(i) := downRegTemp(2+(2*i)).extract(2)
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isSetVal(i) := downRegTemp(2+(2*i)).extract(3)
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mode(i) := downRegTemp(2+(2*i))(5,4)
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invDirect(i) := downRegTemp(2+(2*i)).extract(6)
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isSign(i) := downRegTemp(2+(2*i)).extract(7)
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}
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when( (isCrcPass & downRegTemp(0)(3,0) === 0.U) & ~downRegTemp(2+i).extract(3) ){
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initVal(i) := 0.U
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} .elsewhen( (isCrcPass & downRegTemp(0)(3,0) === 0.U) & downRegTemp(2+i).extract(3) ){
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initVal(i) := Cat( downRegTemp(9+(4*i)), downRegTemp(8+(4*i)), downRegTemp(7+(4*i)), downRegTemp(6+(4*i)) )
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}
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}
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val cntLatch = for( i <- 0 until 2 ) yield { RegEnable(counter(i), ~RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) & io.lvdsSlv.upstream_tx_data_ready ) }
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when( statusPage === 0.U ){
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upReg(2) := Cat( isSign(0), invDirect(0), mode(0), isSetVal(0), is2Phase(0), isZPhaseEnable(0), isEnable(0) )
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upReg(3) := 0.U
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upReg(4) := Cat( isSign(1), invDirect(1), mode(1), isSetVal(1), is2Phase(1), isZPhaseEnable(1), isEnable(1) )
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upReg(5) := 0.U
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upReg(6) := cntLatch(0)(7,0)
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upReg(7) := cntLatch(0)(15,8)
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upReg(8) := cntLatch(0)(23,16)
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upReg(9) := cntLatch(0)(31,24)
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upReg(10) := cntLatch(1)(7,0)
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upReg(11) := cntLatch(1)(15,8)
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upReg(12) := cntLatch(1)(23,16)
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upReg(13) := cntLatch(1)(31,24)
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}
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}
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