53 lines
1.0 KiB
Scala
53 lines
1.0 KiB
Scala
package Switch
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import chisel3._
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import chisel3.util._
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class Transmit_Req_Bundle extends Bundle{
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val txLength = UInt(16.W)
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val PerPacketCrcEn = Bool()
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val PerPacketPad = Bool()
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}
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class Transmit_Resp_Bundle extends Bundle{
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val RetryCntLatched = UInt(4.W)
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val RetryLimit = Bool()
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val LateCollLatched = Bool()
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val DeferLatched = Bool()
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val CarrierSenseLost = Bool()
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val isClear = Bool()
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}
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class Transmit_Bundle extends Bundle{
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val data = Decoupled(UInt(32.W))
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val req = Decoupled(new Transmit_Req_Bundle)
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val resp = Flipped(Decoupled(new Transmit_Resp_Bundle))
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}
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class TxBuffIO extends Bundle{
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val enq = Flipped(new Transmit_Bundle)
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val deq = new Transmit_Bundle
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}
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class TxBuff extends Module{
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val io: TxBuffIO = IO(new TxBuffIO)
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io.enq.data.ready := true.B
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io.enq.ctrl.ready := true.B
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io.deq.data.valid := false.B
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io.deq.data.bits := 0.U
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io.deq.req.valid := false.B
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io.deq.req.bits := 0.U.asTypeOf(new Transmit_Deq_Req_Bundle)
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io.deq.resp.ready := true.B
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}
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