154 lines
3.2 KiB
Scala
154 lines
3.2 KiB
Scala
package Switch
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import chisel3._
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import chisel3.util._
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class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule{
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class MacTileLinkMasterIO extends Bundle{
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val A = Decoupled(new TLBundleA(edgeOut.bundle))
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val D = Flipped(Decoupled(new TLBundleD(edgeOut.bundle)))
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}
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class SwitchMuxIO(implicit p: Parameters) extends SwitchBundle{
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val dmaMst = new MacTileLinkMasterIO
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val triTx = Input(Bool())
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val rxEnq = Vec(chn, new Receive_Enq_Bundle)
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val txDeq = Vec(chn, Flipped(new Transmit_Deq_Bundle))
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}
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val io: SwitchMuxIO = IO(new SwitchMuxIO)
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def stateIdle = 0.U
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def stateRx = 1.U
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def stateTx = 2.U
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val stateNxt = Wire(UInt(2.W))
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val stateCur = RegNext(stateNxt, stateIdle)
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stateNxt :=
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Mux1H(Seq(
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( stateCur === stateIdle ) -> Mux( rxBuff.io.deq.header.fire, stateRx, Mux( txBuff.io.enq.req.fire, stateTx, stateIdle ) ),
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( stateCur === stateRx ) -> Mux( rxBuff.io.deq.ctrl.fire, stateIdle, stateRx ),
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( stateCur === stateTx ) -> Mux( txBuff.io.enq.resp.fire, stateIdle, stateTx ),
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))
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def ptr = 0x8002000
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def txLength = 8
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def PerPacketCrcEn = true.B
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def PerPacketPad = true.B
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val rxBuff = Module(new RxBuff)
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rxBuff.io.enq <> io.rxEnq(0)
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val txBuff = Module(new TxBuff)
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txBuff.io.deq <> mac.io.txDeq(0)
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rxBuff.io.deq.ctrl.ready := stateCur === stateRx
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val txReqValid = RegInit(false.B)
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when( txBuff.io.enq.req.fire ){
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txReqValid := false.B
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} .elsewhen( io.triTx ){
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txReqValid := true.B
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}
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txBuff.io.enq.req.valid := txReqValid && stateCur === stateIdle
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txBuff.io.enq.bits.txLength := txLength
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txBuff.io.enq.bits.PerPacketCrcEn := PerPacketCrcEn
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txBuff.io.enq.bits.PerPacketPad := PerPacketPad
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txBuff.io.enq.resp.ready := true.B
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val dmaTxAValid = RegInit(false.B)
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val dmaTxABits = Reg(new TLBundleA(edgeOut.bundle))
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val dmaAddress = Reg( UInt(32.W) )
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when( stateCur === stateIdle && stateNxt =/= stateIdle ){
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dmaAddress := ptr.U
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} .elsewhen( io.A.fire ){
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dmaAddress := dmaAddress + 4.U
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}
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rxBuff.io.deq.data.ready := io.A.ready & stateCur === stateRx
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rxBuff.io.deq.header.ready := ~io.io.triTx && ~txReqValid
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when( io.A.fire ){
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dmaTxAValid := false.B
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} .elsewhen( txBuff.io.enq.req.fire ){
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dmaTxAValid := true.B
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dmaTxABits :=
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edgeOut.Get(
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fromSource = 0.U,
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toAddress = dmaAddress >> 2 << 2,
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lgSize = log2Ceil(txLength).U,
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)._2
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}
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io.A.valid :=
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Mux1H(Seq(
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stateCur === stateRx -> rxBuff.io.deq.data.valid,
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stateCur === stateTx -> dmaTxAValid,
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))
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when( stateCur === stateRx ){
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io.A.bits :=
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edgeOut.Put(
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fromSource = 0.U,
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toAddress = dmaAddress >> 2 << 2,
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lgSize = log2Ceil(32/8).U,
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data = rxBuff.io.deq.data.bits,
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mask = "b1111".U,
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)._2
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} .elsewhen( stateCur === stateTx ){
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io.A.bits := dmaTxABits
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} .otherwise{
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io.A.bits := DontCare
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}
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txBuff.io.enq.data.valid := io.D.valid & stateCur === stateTx
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txBuff.io.enq.data.bits := io.D.bits.data
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io.D.ready :=
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Mux1H(Seq(
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stateCur === stateRx -> true.B,
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stateCur === stateTx -> txBuff.io.enq.data.ready,
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))
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}
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