107 lines
4.1 KiB
Scala
107 lines
4.1 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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// module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
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// input Clk;
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// input Reset;
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// input [3:0] Data;
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// input Enable;
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// input Initialize;
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// output [31:0] Crc;
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// output CrcError;
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// reg [31:0] Crc;
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// wire [31:0] CrcNext;
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// assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);
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// assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);
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// assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);
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// assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);
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// assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];
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// assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];
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// assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];
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// assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];
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// assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];
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// assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];
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// assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];
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// assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];
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// assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];
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// assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];
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// assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];
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// assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];
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// assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];
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// assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];
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// assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];
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// assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];
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// assign CrcNext[20] = Crc[16];
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// assign CrcNext[21] = Crc[17];
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// assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];
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// assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];
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// assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];
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// assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];
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// assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];
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// assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];
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// assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];
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// assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];
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// assign CrcNext[30] = Crc[26];
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// assign CrcNext[31] = Crc[27];
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// always @ (posedge Clk or posedge Reset)
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// begin
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// if (Reset)
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// Crc <= 32'hffffffff;
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// else
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// if(Initialize)
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// Crc <= 32'hffffffff;
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// else
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// Crc <= CrcNext;
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// end
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// assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
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// endmodule
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//-----------------------------------------------------------------------------
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// Copyright (C) 2009 OutputLogic.com
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// This source file may be used and distributed without restriction
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// provided that this copyright statement is not removed from the file
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// and that any derivative work contains the original copyright notice
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// and the associated disclaimer.
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//
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// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
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// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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//-----------------------------------------------------------------------------
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// CRC module for data[7:0] , crc[31:0]=1+x^1+x^2+x^4+x^5+x^7+x^8+x^10+x^11+x^12+x^16+x^22+x^23+x^26+x^32;
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//-----------------------------------------------------------------------------
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class crc32_8() extends Module{
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class crc32IO_Bundle extends Bundle{
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val isEnable = Input(Bool())
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val dataIn = Input(UInt(8.W))
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val crc = Output(UInt(32.W))
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}
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val io = IO( new crc32IO_Bundle )
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// val LFSR_POLY = "h4c11db7".U
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io.crc := "ha1b2c3d4".U
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}
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