Files
eb001/src/main/verilog/defineParam.v
2024-09-02 16:24:02 +08:00

5 lines
142 B
Verilog

`define VENDORID 16'h1122
`define MODULEID 16'h3344
`define HWVERSION 16'h5566
`define SWVERSION 16'h7788
`define SERIAL 48'hbbccddeeff00