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b9d255b7ce627de09eb8261d5a342355f1722b25
eb001
/
src
/
main
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Ruige Lee
d7146a786b
cdrout 每128byte发送无意义“b0000000010”用于解锁cdrin并重新上锁
...
需要配平fifo,覆盖每个长度端,长度边缘,解锁在crc位置,不同preamble长度
2025-08-19 17:04:58 +08:00
..
resources
增加顶层的FPGA上的sync输出,修改测试用例
2025-08-11 18:04:46 +08:00
scala
cdrout 每128byte发送无意义“b0000000010”用于解锁cdrin并重新上锁
2025-08-19 17:04:58 +08:00
verilog
高云FPGA:dout新检测特性;删除退役的版本
2025-03-12 17:36:10 +08:00