140 lines
3.3 KiB
Scala
140 lines
3.3 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class SimCDR extends Module with RequireAsyncReset{
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val io = IO(new Bundle{
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val data = Input( UInt(8.W) )
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val multiCLK = Input(Vec(16, Bool()))
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val flush = Input(Bool())
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val isSuccess = Output(Bool())
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val isFailed = Output(Bool())
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})
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val cdrInAxis = Module(new CDRInAxis)
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val cdrInSample = Module(new CDRInMultiSample)
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val cdrOut = Module(new CDROut)
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val record = Module( new Queue(UInt(8.W), 256) )
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val dataCnt = RegInit(0.U(12.W))
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val payloadLen = RegInit(("hFFF".U)(12.W))
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val b4b5Encoder = Module(new b4b5DualEncode)
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val b4b5Decoder = Module(new b4b5DualDecode)
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val b8b10Encoder = Module(new b8b10Encode)
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val b8b10Decoder = Module(new b8b10Decode)
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when( cdrOut.io.axis.fire & dataCnt === 0.U ){
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payloadLen := Cat( io.data, 0.U(4.W) )
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} .elsewhen( cdrOut.io.axis.fire & dataCnt === 1.U ){
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payloadLen := Cat( payloadLen(11,4), io.data(7,4) ) + 4.U + 4.U
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}
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when( cdrOut.io.axis.fire ){
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when( dataCnt >= payloadLen - 1.U ){
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dataCnt := 0.U
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} .otherwise{
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dataCnt := dataCnt + 1.U
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}
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}
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cdrOut.io.flush := io.flush
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cdrInAxis.clock := io.multiCLK(0).asClock
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cdrInSample.clock := io.multiCLK(0).asClock
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cdrInAxis.io.flush := io.flush
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cdrInSample.multiCLK := io.multiCLK
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cdrInAxis.io.syncSerDat := cdrInSample.io.syncSerDat
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cdrInSample.io.serDat := cdrOut.io.serDat
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assert( ~(record.io.enq.valid & ~record.io.enq.ready), "Assert Failed, Warning, fifo overflow!\n" )
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assert( ~(~record.io.deq.valid & record.io.deq.ready), "Assert Failed, Warning, fifo underflow!\n" )
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val isTxEnd = cdrOut.io.axis.fire & cdrOut.io.axis.bits.tlast
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cdrOut.io.axis.valid := ~io.flush & ShiftRegisters( ~isTxEnd, 16 ).reduce(_&_)
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cdrOut.io.axis.bits.tdata := io.data
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cdrOut.io.axis.bits.tuser := false.B
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cdrOut.io.axis.bits.tlast := dataCnt === (payloadLen - 1.U)
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record.io.enq.valid := cdrOut.io.axis.fire
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record.io.enq.bits := io.data
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record.io.deq.ready := cdrInAxis.io.axis.fire
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cdrInAxis.io.axis.ready := true.B
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io.isFailed := cdrInAxis.io.axis.fire & (record.io.deq.bits =/= cdrInAxis.io.axis.bits.tdata)
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io.isSuccess := cdrInAxis.io.axis.fire & cdrInAxis.io.axis.bits.tlast
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val isUsing8b10b = false.B
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when( isUsing8b10b ){
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b8b10Encoder.io <> cdrOut.io.encode
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b8b10Decoder.io <> cdrInAxis.io.decode
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b4b5Encoder.io.isEnable := false.B
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b4b5Encoder.io.dataIn := 0.U
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b4b5Decoder.io.dataIn := 0.U
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} .otherwise{
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b4b5Encoder.io <> cdrOut.io.encode
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b4b5Decoder.io <> cdrInAxis.io.decode
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b8b10Encoder.io.isEnable := false.B
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b8b10Encoder.io.dataIn := 0.U
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b8b10Decoder.io.dataIn := 0.U
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}
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// val coverData = RegInit(VecInit(Seq.fill(512){false.B}))
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// when( record.io.enq.fire ){
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// for( i <- 0 until 256 ){
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// when( record.io.enq.bits === i.U ){
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// when( b8b10Encoder.rdTest ){
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// coverData(i) := true.B
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// } .otherwise{
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// coverData(256+i) := true.B
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// }
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// }
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// }
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// }
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val coverData = RegInit(VecInit(Seq.fill(256){false.B}))
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when( record.io.enq.fire ){
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for( i <- 0 until 256 ){
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when( record.io.enq.bits === i.U ){
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coverData(i) := true.B
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}
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}
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}
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val coverage = PopCount(coverData.asUInt)
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when( io.isSuccess ){
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printf( cf"Coverage: ${coverage}\n")
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}
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}
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