70 lines
1.4 KiB
Scala
70 lines
1.4 KiB
Scala
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package Switch
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import chisel3._
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import chisel3.util._
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import chisel3.util.random._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import MAC._
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class Robin_Bundle(implicit p: Parameters) extends SwitchBundle{
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val rx = Decoupled(new Mac_Stream_Bundle)
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val mInfo = new Rx_MuxInfo_Bundle
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}
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class Robin(implicit p: Parameters) extends SwitchModule{
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class RobinIO extends Bundle{
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val enq = Vec( chn+1, Flipped(new Robin_Bundle) )
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val deq = new Robin_Bundle
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val sel = Output(UInt( (log2Ceil(chn+1)).W ))
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}
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val io: RobinIO = IO(new RobinIO)
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val isLock = RegInit(false.B)
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val lockChn = Reg(UInt((log2Ceil(chn+1)).W))
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io.sel := lockChn
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val lfsr = ~LFSR( (log2Ceil(chn+1)+1), ~isLock)
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for( i <- 0 until chn+1 ) {
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when( i.U === lfsr ){
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when( io.enq(i).mInfo.dest.valid ){
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assert( ~isLock )
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isLock := true.B
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lockChn := lfsr
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}
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}
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}
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when( io.deq.rx.fire & io.deq.rx.bits.isLast ){
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assert( isLock )
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isLock := false.B
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}
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for( i <- 0 until chn+1 ) {
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io.enq(i).rx.ready := false.B
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}
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when( ~isLock ){
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io.deq.rx.valid := false.B
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io.deq.rx.bits := 0.U.asTypeOf(new Mac_Stream_Bundle)
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io.deq.mInfo.dest.valid := false.B
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io.deq.mInfo.dest.bits := 0.U
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io.deq.mInfo.source.valid := false.B
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io.deq.mInfo.source.bits := 0.U
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} .otherwise{
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io.deq <> io.enq(lockChn)
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}
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} |