43 lines
1.1 KiB
Scala
43 lines
1.1 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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class SimpleGpio()(implicit p: Parameters) extends BackModule{
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class SimpleGpioIO extends Bundle{
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val mem = Flipped(new Mem_Port_Bundle)
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val out = Output(UInt(32.W))
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val in = Input(UInt(32.W))
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val isOnline = Output(Bool())
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val isLast = Input(Bool())
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}
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val io: SimpleGpioIO = IO(new SimpleGpioIO)
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val isWriteGpio = io.mem.fire & io.mem.addr(3,0) === "h0".U & io.mem.wstrb =/= 0.U
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val isReadGpio = io.mem.fire & io.mem.addr(3,0) === "h0".U & io.mem.wstrb === 0.U
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// val isWriteDir = io.mem.fire & io.mem.addr(3,0) === "h4".U & io.mem.wstrb =/= 0.U
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val isReadIsLast = io.mem.fire & io.mem.addr(3,0) === "h8".U & io.mem.wstrb === 0.U
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io.isOnline := false.B
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io.out := RegEnable( io.mem.wdata, 0.U(32.W), isWriteGpio )
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io.mem.ready := true.B
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io.mem.rdata :=
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Mux( io.mem.addr(3,0) === "h0".U, io.in,
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Mux( io.mem.addr(3,0) === "h8".U, io.isLast, 0.U ) )
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}
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