56 lines
1.5 KiB
Scala
56 lines
1.5 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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class SimpleSRAM()(implicit p: Parameters) extends BackModule{
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class SimpleSRAMIO extends Bundle{
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val mem = Flipped(new Mem_Port_Bundle)
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}
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val io: SimpleSRAMIO = IO(new SimpleSRAMIO)
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val mem = SyncReadMem(1024, Vec(4, UInt(8.W)))
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io.mem.rdata := DontCare
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// when(io.mem.valid) {
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mem.write(
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io.mem.addr(11,2),
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VecInit( io.mem.wdata(31,24), io.mem.wdata(23,16), io.mem.wdata(15,8), io.mem.wdata(7,0) ),
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VecInit( io.mem.valid & io.mem.wstrb.extract(3), io.mem.valid & io.mem.wstrb.extract(2), io.mem.valid & io.mem.wstrb.extract(1), io.mem.valid & io.mem.wstrb.extract(0) )
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)
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io.mem.rdata := Cat( mem.read(io.mem.addr(11,2), true.B).reverse )
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// when ( io.mem.wstrb =/= 0.U ) {
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// when(io.mem.wstrb.extract(0)) { mem(io.mem.addr(11,2))(0) := io.mem.wdata(7,0) }
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// when(io.mem.wstrb.extract(1)) { mem(io.mem.addr(11,2))(1) := io.mem.wdata(15,8) }
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// when(io.mem.wstrb.extract(2)) { mem(io.mem.addr(11,2))(2) := io.mem.wdata(23,16) }
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// when(io.mem.wstrb.extract(3)) { mem(io.mem.addr(11,2))(3) := io.mem.wdata(31,24) }
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// } .otherwise { io.mem.rdata := Cat( mem(io.mem.addr(11,2)).reverse ) }
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// }
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val isAck = RegInit(false.B)
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when( io.mem.fire ){
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isAck := false.B
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} .elsewhen( io.mem.valid & ~isAck ){
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isAck := true.B
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}
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io.mem.ready := isAck
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} |