97 lines
1.9 KiB
Verilog
97 lines
1.9 KiB
Verilog
`timescale 1 ns / 1 ps
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module SimCDRTb(
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);
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reg clock = 0;
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reg reset = 0;
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reg [15:0] multiCLK;
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initial begin
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clock = 0;
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reset = 1;
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#100
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reset <= 1;
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#240
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reset <= 0;
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end
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initial begin
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forever begin #80 clock <= ~clock; end
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end
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generate
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for( genvar i = 0; i < 16; i = i + 1 ) begin
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initial begin
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multiCLK[i] = 0;
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for( integer j = 0; j < i; j = j + 1 ) begin
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#20
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;
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end
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forever begin #80 multiCLK[i] <= ~multiCLK[i]; end
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end
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end
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endgenerate
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reg [7:0] data;
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wire success;
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wire failed;
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always @(posedge clock) begin
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data <= $random;
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end
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SimCDR s_SimCDR(
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.clock(clock),
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.reset(reset),
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.io_data(data),
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.io_multiCLK_0(multiCLK[0]),
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.io_multiCLK_1(multiCLK[1]),
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.io_multiCLK_2(multiCLK[2]),
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.io_multiCLK_3(multiCLK[3]),
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.io_multiCLK_4(multiCLK[4]),
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.io_multiCLK_5(multiCLK[5]),
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.io_multiCLK_6(multiCLK[6]),
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.io_multiCLK_7(multiCLK[7]),
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.io_multiCLK_8(multiCLK[8]),
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.io_multiCLK_9(multiCLK[9]),
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.io_multiCLK_10(multiCLK[10]),
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.io_multiCLK_11(multiCLK[11]),
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.io_multiCLK_12(multiCLK[12]),
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.io_multiCLK_13(multiCLK[13]),
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.io_multiCLK_14(multiCLK[14]),
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.io_multiCLK_15(multiCLK[15]),
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.io_flush(1'b0),
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.io_isSuccess(success),
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.io_isFailed(failed)
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);
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initial
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begin
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$dumpfile("./tb/build/wave_cdr.vcd"); //生成的vcd文件名称
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$dumpvars(0, SimCDRTb);//tb模块名称
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end
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always @(posedge clock) begin
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if (success) begin
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$display("Success onces! \n");
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end
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if (failed) begin
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$display("Error! \n");
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$stop;
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end
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end
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endmodule
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