70 lines
1.4 KiB
Verilog
70 lines
1.4 KiB
Verilog
module CDROne_fpga(
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input clock,
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input resetn,
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output [7:0] led
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// output serDat_o_p,
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// output serDat_o_n,
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// input serDat_i_p,
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// input serDat_i_n
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);
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wire serDat_o;
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wire serDat_i;
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wire clk100;
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wire clk400;
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// IBUFDS #(
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// .DIFF_TERM("FALSE"), // Differential Termination
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// .IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
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// .IOSTANDARD("DEFAULT") // Specify the input I/O standard
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// ) IBUFDS_inst (
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// .O(serDat_i), // Buffer output
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// .I(serDat_i_p), // Diff_p buffer input (connect directly to top-level port)
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// .IB(serDat_i_n) // Diff_n buffer input (connect directly to top-level port)
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// );
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// OBUFDS #(
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// .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
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// .SLEW("SLOW") // Specify the output slew rate
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// ) OBUFDS_inst (
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// .O(serDat_o_p), // Diff_p output (connect directly to top-level port)
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// .OB(serDat_o_n), // Diff_n output (connect directly to top-level port)
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// .I(serDat_o) // Buffer input
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// );
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clk_wiz_0
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(
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// Clock out ports
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.clk_out1(clk100),
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.clk_out2(clk400),
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// Clock in ports
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.clk_in1(clock)
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);
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CDROut_fpga(
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.clock(clk100),
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.reset(~resetn),
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.serDat(serDat_o)
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);
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CDRIn_fpga(
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.clock(clk100),
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.reset(~resetn),
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.overCLK(clk400),
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.serDat(serDat_o),
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// .serDat(serDat_i),
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.led(led)
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);
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endmodule
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