682 lines
23 KiB
Scala
682 lines
23 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class TopBase_IO_Bundle extends Bundle{
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val dDatIn = Input(Bool())
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val dDatOut = Output(Bool())
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val uDatIn = Input(Bool())
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val uDatOut = Output(Bool())
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val iqspi = new QSPIInterfaceIO
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val ospi = new SSPIInterfaceIO
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val oqspi = new QSPIInterfaceIO
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val aqspi = new QSPIInterfaceIO
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val iSync = Output(Vec(4, Bool()))
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val isSoftReset = Output(Bool())
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val interrupt = Output(Bool())
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val latchPin = Input(Vec(2, Bool()))
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val hwSerial = Input(UInt(48.W))
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val uniCode = Input(UInt(64.W))
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val pllCtrl = Output(UInt(32.W))
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val xtal = Output(UInt(12.W))
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val anamuxSel = Output(UInt(5.W))
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val ldo2p5 = Output(UInt(8.W))
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val ldo1p1 = Output(UInt(8.W))
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val refTop = Output(UInt(3.W))
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val bias = Output(UInt(2.W))
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val div4 = Output(UInt(4.W))
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val spiSel = Output(UInt(2.W))
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val isPllCfg = Output(Bool())
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}
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class MstSlvSwitchIO extends TopBase_IO_Bundle{
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val downCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) )
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val upCDRSampleIn = Vec(3, Flipped(new CDRInSampleIO) )
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}
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abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
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val io: MstSlvSwitchIO = IO(new MstSlvSwitchIO)
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val downCDROut = Module(new CDROut)
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val upCDROut = Module(new CDROut)
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val downCDRInAxis = Module(new CDRInAxis)
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val upCDRInAxis = Module(new CDRInAxis)
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val slaveParser = Module(new SlaveParser )
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val masterParser = Module(new MasterParser)
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val b4b5DownEncoder = Module(new b4b5DualEncode)
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val b4b5DownDecoder = Module(new b4b5DualDecode)
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val b4b5UpEncoder = Module(new b4b5DualEncode)
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val b4b5UpDecoder = Module(new b4b5DualDecode)
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val b8b10DownEncoder = Module(new b8b10Encode)
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val b8b10DownDecoder = Module(new b8b10Decode)
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val b8b10UpEncoder = Module(new b8b10Encode)
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val b8b10UpDecoder = Module(new b8b10Decode)
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val interface = Module(new Interface)
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val downInSerDat = Wire(Bool())
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val downInSyncSerDat = Wire(Bool()); downCDRInAxis.io.syncSerDat := downInSyncSerDat
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val upInSerDat = Wire(Bool())
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val upInSyncSerDat = Wire(Bool()); upCDRInAxis.io.syncSerDat := upInSyncSerDat
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dontTouch(downInSerDat)
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dontTouch(downInSyncSerDat)
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dontTouch(upInSerDat)
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dontTouch(upInSyncSerDat)
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interface.io.latchPin := io.latchPin
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interface.io.uniCode := io.uniCode
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interface.io.hwSerial := io.hwSerial
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interface.io.intTransEnd(0) := downCDRInAxis.io.axis.fire & downCDRInAxis.io.axis.bits.tlast
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interface.io.intTransEnd(1) := downCDROut.io.axis.fire & downCDROut.io.axis.bits.tlast
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interface.io.intTransEnd(2) := upCDRInAxis.io.axis.fire & upCDRInAxis.io.axis.bits.tlast
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interface.io.intTransEnd(3) := upCDROut.io.axis.fire & upCDROut.io.axis.bits.tlast
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io.isSoftReset := interface.io.isSoftReset
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io.interrupt := interface.io.interrupt
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io.ospi <> interface.io.ospi
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io.iqspi <> interface.io.iqspi
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io.oqspi <> interface.io.oqspi
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io.aqspi <> interface.io.aqspi
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io.iSync := interface.io.sync
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io.pllCtrl := interface.io.cReg.pllCtrl
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io.xtal := interface.io.cReg.xtal
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io.anamuxSel := interface.io.cReg.anamuxSel
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io.ldo2p5 := interface.io.cReg.ldo2p5
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io.ldo1p1 := interface.io.cReg.ldo1p1
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io.refTop := interface.io.cReg.refTop
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io.bias := interface.io.cReg.bias
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io.div4 := interface.io.cReg.div4
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io.spiSel := interface.io.cReg.spiSel
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io.isPllCfg := interface.io.isPllCfg
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val sram = Seq(
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for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
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for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
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for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
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for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
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for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
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for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
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for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
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for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
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)
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val smUnit = Seq(
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Module( new SMUnit(depth = 4) ),
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Module( new SMUnit(depth = 4) ),
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Module( new SMUnit(depth = 4) ),
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Module( new SMUnit(depth = 4) ),
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Module( new SMUnit(depth = 2) ),
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Module( new SMUnit(depth = 2) ),
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Module( new SMUnit(depth = 2) ),
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Module( new SMUnit(depth = 2) ),
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)
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val lvdsSMEnq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMEnq := lvdsSMEnq
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val lvdsSMDeq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMDeq := lvdsSMDeq
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val lvdsSMComf = for( i <- 0 until 4 ) yield WireDefault(false.B)
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val lvdsSMAbrt = for( i <- 0 until 4 ) yield WireDefault(false.B)
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smUnit(0).io.enq := lvdsSMEnq(0)
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smUnit(2).io.enq := lvdsSMEnq(1)
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smUnit(4).io.enq := lvdsSMEnq(2)
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smUnit(6).io.enq := lvdsSMEnq(3)
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smUnit(0).io.isComf := lvdsSMComf(0)
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smUnit(2).io.isComf := lvdsSMComf(1)
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smUnit(4).io.isComf := lvdsSMComf(2)
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smUnit(6).io.isComf := lvdsSMComf(3)
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smUnit(0).io.isAbrt := lvdsSMAbrt(0)
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smUnit(2).io.isAbrt := lvdsSMAbrt(1)
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smUnit(4).io.isAbrt := lvdsSMAbrt(2)
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smUnit(6).io.isAbrt := lvdsSMAbrt(3)
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smUnit(1).io.deq := lvdsSMDeq(0)
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smUnit(3).io.deq := lvdsSMDeq(1)
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smUnit(5).io.deq := lvdsSMDeq(2)
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smUnit(7).io.deq := lvdsSMDeq(3)
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smUnit(0).io.sram_r <> interface.io.sram_r(0)
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smUnit(2).io.sram_r <> interface.io.sram_r(1)
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smUnit(4).io.sram_r <> interface.io.sram_r(2)
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smUnit(6).io.sram_r <> interface.io.sram_r(3)
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smUnit(1).io.sram_w := interface.io.sram_w(0)
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smUnit(3).io.sram_w := interface.io.sram_w(1)
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smUnit(5).io.sram_w := interface.io.sram_w(2)
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smUnit(7).io.sram_w := interface.io.sram_w(3)
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smUnit(0).io.deq := interface.io.dSMdeq(0)
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smUnit(2).io.deq := interface.io.dSMdeq(1)
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smUnit(4).io.deq := interface.io.dSMdeq(2)
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smUnit(6).io.deq := interface.io.dSMdeq(3)
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smUnit(1).io.enq := interface.io.uSMenq(0)
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smUnit(3).io.enq := interface.io.uSMenq(1)
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smUnit(5).io.enq := interface.io.uSMenq(2)
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smUnit(7).io.enq := interface.io.uSMenq(3)
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smUnit(1).io.isComf := RegNext( smUnit(1).io.enq, false.B )
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smUnit(3).io.isComf := RegNext( smUnit(3).io.enq, false.B )
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smUnit(5).io.isComf := RegNext( smUnit(5).io.enq, false.B )
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smUnit(7).io.isComf := RegNext( smUnit(7).io.enq, false.B )
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smUnit(1).io.isAbrt := false.B
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smUnit(3).io.isAbrt := false.B
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smUnit(5).io.isAbrt := false.B
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smUnit(7).io.isAbrt := false.B
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for( i <- 0 until 8 ){
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interface.io.smUsedDepth(i) := smUnit(i).io.cnt
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smUnit(i).io.flush := interface.io.isSMReset(i)
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}
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for( i <- 0 until 4 ){
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for( j <- 0 until 4 ){
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sram(i)(j).io.clockr := clock.asBool
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sram(i)(j).io.clockw := clock.asBool
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smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
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sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
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sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
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sram(i)(j).io.enw := smUnit(i).io.sram(j).wr.enw
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sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
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sram(i)(j).io.enr := smUnit(i).io.sram(j).rd.enr
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}
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}
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for( i <- 4 until 8 ){
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for( j <- 0 until 2 ){
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sram(i)(j).io.clockr := clock.asBool
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sram(i)(j).io.clockw := clock.asBool
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smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
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sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
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sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
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sram(i)(j).io.enw := smUnit(i).io.sram(j).wr.enw
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sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
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sram(i)(j).io.enr := smUnit(i).io.sram(j).rd.enr
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}
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}
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//default
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{
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smUnit(0).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
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smUnit(2).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
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smUnit(4).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
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smUnit(6).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
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smUnit(1).io.sram_r.enr := false.B
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smUnit(3).io.sram_r.enr := false.B
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smUnit(5).io.sram_r.enr := false.B
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smUnit(7).io.sram_r.enr := false.B
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smUnit(1).io.sram_r.addrr := 0.U
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smUnit(3).io.sram_r.addrr := 0.U
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smUnit(5).io.sram_r.addrr := 0.U
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smUnit(7).io.sram_r.addrr := 0.U
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slaveParser.io.sram_r(0).datar := 0.U
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slaveParser.io.sram_r(1).datar := 0.U
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slaveParser.io.sram_r(2).datar := 0.U
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slaveParser.io.sram_r(3).datar := 0.U
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masterParser.io.sram_r.datar := 0.U
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downCDRInAxis.io.axis.ready := false.B
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slaveParser.io.downIn.valid := false.B
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slaveParser.io.downIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
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slaveParser.io.downOut.ready := false.B
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masterParser.io.downOut.ready := false.B
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downCDROut.io.axis.valid := false.B
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downCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
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upCDRInAxis.io.axis.ready := false.B
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slaveParser.io.upIn.valid := false.B
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slaveParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
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masterParser.io.upIn.valid := false.B
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masterParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
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slaveParser.io.upOut.ready := false.B
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upCDROut.io.axis.valid := false.B
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upCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
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interface.io.mstDeltaTime := 0.U
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interface.io.slvDeltaTime := 0.U
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interface.io.deltaFinal := 0.U
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interface.io.intMstTrig(0) := false.B
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interface.io.intMstTrig(1) := false.B
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interface.io.intSlvTrig(0) := false.B
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interface.io.intSlvTrig(1) := false.B
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interface.io.intSlvTrig(2) := false.B
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interface.io.intSlvTrig(3) := false.B
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interface.io.intSlvTrig(4) := false.B
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interface.io.intSlvTrig(5) := false.B
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interface.io.intSlvTrig(6) := false.B
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interface.io.intSlvTrig(7) := false.B
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interface.io.intHWTrig(0) := false.B
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interface.io.intHWTrig(1) := false.B
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interface.io.downRecStat := 0.U.asTypeOf(new Stat_IO_Bundle)
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interface.io.upRecStat := 0.U.asTypeOf(new Stat_IO_Bundle)
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}
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}
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trait MstSlvSwitchMaster{ this: MstSlvSwitchBase =>
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when( interface.io.cReg.modeSel === true.B ){
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masterParser.io.downOut <> downCDROut.io.axis
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masterParser.io.upIn <> upCDRInAxis.io.axis
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}
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when( interface.io.cReg.modeSel === true.B ){
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when( interface.io.txReq.bits.rxSM === 0.U ){
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smUnit(0).io.sram_w := masterParser.io.sram_w
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lvdsSMEnq(0) := masterParser.io.rxEnq
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lvdsSMComf(0) := RegNext(masterParser.io.rxEnq, false.B)
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lvdsSMAbrt(0) := false.B
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} .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){
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smUnit(2).io.sram_w := masterParser.io.sram_w
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lvdsSMEnq(1) := masterParser.io.rxEnq
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lvdsSMComf(1) := RegNext(masterParser.io.rxEnq, false.B)
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lvdsSMAbrt(1) := false.B
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} .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){
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smUnit(4).io.sram_w := masterParser.io.sram_w
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lvdsSMEnq(2) := masterParser.io.rxEnq
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lvdsSMComf(2) := RegNext(masterParser.io.rxEnq, false.B)
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lvdsSMAbrt(2) := false.B
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} .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){
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smUnit(6).io.sram_w := masterParser.io.sram_w
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lvdsSMEnq(3) := masterParser.io.rxEnq
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lvdsSMComf(3) := RegNext(masterParser.io.rxEnq, false.B)
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lvdsSMAbrt(3) := false.B
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}
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when( interface.io.txReq.bits.txSM === 0.U ){
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smUnit(1).io.sram_r <> masterParser.io.sram_r
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lvdsSMDeq(0) := masterParser.io.txDeq
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} .elsewhen( interface.io.txReq.bits.txSM === 1.U ){
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smUnit(3).io.sram_r <> masterParser.io.sram_r
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lvdsSMDeq(1) := masterParser.io.txDeq
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} .elsewhen( interface.io.txReq.bits.txSM === 2.U ){
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smUnit(5).io.sram_r <> masterParser.io.sram_r
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lvdsSMDeq(2) := masterParser.io.txDeq
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} .elsewhen( interface.io.txReq.bits.txSM === 3.U ){
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smUnit(7).io.sram_r <> masterParser.io.sram_r
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lvdsSMDeq(3) := masterParser.io.txDeq
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}
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interface.io.mstDeltaTime := masterParser.io.deltaTimeStamp
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interface.io.intMstTrig(0) := masterParser.io.txDeq
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interface.io.intMstTrig(1) := masterParser.io.rxEnq
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interface.io.downRecStat := 0.U.asTypeOf(new Stat_IO_Bundle)
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interface.io.upRecStat := masterParser.io.upRecStat
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}
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masterParser.io.req := interface.io.txReq.valid
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masterParser.io.cReg := interface.io.cReg
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masterParser.io.mReg := interface.io.mReg
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}
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trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>
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when( interface.io.cReg.modeSel === false.B ){
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slaveParser.io.downIn <> downCDRInAxis.io.axis
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downCDROut.io.axis <> slaveParser.io.downOut
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slaveParser.io.upIn <> upCDRInAxis.io.axis
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upCDROut.io.axis <> slaveParser.io.upOut
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}
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slaveParser.io.cReg := interface.io.cReg
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slaveParser.io.sReg := interface.io.sReg
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when( interface.io.cReg.modeSel === false.B ){
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smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
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smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
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smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
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smUnit(6).io.sram_w := slaveParser.io.sram_w(3)
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smUnit(1).io.sram_r <> slaveParser.io.sram_r(0)
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smUnit(3).io.sram_r <> slaveParser.io.sram_r(1)
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smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
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smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)
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lvdsSMEnq(0) := slaveParser.io.dSMenq(0)
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lvdsSMEnq(1) := slaveParser.io.dSMenq(1)
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lvdsSMEnq(2) := slaveParser.io.dSMenq(2)
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lvdsSMEnq(3) := slaveParser.io.dSMenq(3)
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lvdsSMComf(0) := slaveParser.io.downRecStat.isFinish
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lvdsSMComf(1) := slaveParser.io.downRecStat.isFinish
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lvdsSMComf(2) := slaveParser.io.downRecStat.isFinish
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lvdsSMComf(3) := slaveParser.io.downRecStat.isFinish
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lvdsSMAbrt(0) := slaveParser.io.downRecStat.isRecError
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lvdsSMAbrt(1) := slaveParser.io.downRecStat.isRecError
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||
lvdsSMAbrt(2) := slaveParser.io.downRecStat.isRecError
|
||
lvdsSMAbrt(3) := slaveParser.io.downRecStat.isRecError
|
||
|
||
lvdsSMDeq(0) := slaveParser.io.uSMdeq(0)
|
||
lvdsSMDeq(1) := slaveParser.io.uSMdeq(1)
|
||
lvdsSMDeq(2) := slaveParser.io.uSMdeq(2)
|
||
lvdsSMDeq(3) := slaveParser.io.uSMdeq(3)
|
||
|
||
interface.io.mstDeltaTime := slaveParser.io.mstDeltaTimeStamp
|
||
interface.io.slvDeltaTime := slaveParser.io.slvDeltaTime
|
||
interface.io.deltaFinal := slaveParser.io.deltaFinal
|
||
|
||
interface.io.intSlvTrig(0) := slaveParser.io.dSMenq(0)
|
||
interface.io.intSlvTrig(1) := slaveParser.io.uSMdeq(0)
|
||
interface.io.intSlvTrig(2) := slaveParser.io.dSMenq(1)
|
||
interface.io.intSlvTrig(3) := slaveParser.io.uSMdeq(1)
|
||
interface.io.intSlvTrig(4) := slaveParser.io.dSMenq(2)
|
||
interface.io.intSlvTrig(5) := slaveParser.io.uSMdeq(2)
|
||
interface.io.intSlvTrig(6) := slaveParser.io.dSMenq(3)
|
||
interface.io.intSlvTrig(7) := slaveParser.io.uSMdeq(3)
|
||
|
||
interface.io.intHWTrig(0) := slaveParser.io.intHWTrig(0)
|
||
interface.io.intHWTrig(1) := slaveParser.io.intHWTrig(1)
|
||
|
||
|
||
interface.io.downRecStat := slaveParser.io.downRecStat
|
||
interface.io.upRecStat := slaveParser.io.upRecStat
|
||
|
||
}
|
||
|
||
slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0)
|
||
slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1)
|
||
downCDRInAxis.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B )
|
||
upCDRInAxis.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B )
|
||
downCDROut.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B )
|
||
upCDROut.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B )
|
||
|
||
interface.io.lvds <> slaveParser.io.lvds
|
||
|
||
interface.io.localDevIndex := slaveParser.io.localDevIndex
|
||
|
||
//从站链路寄存器
|
||
interface.io.isDevOnRight := slaveParser.io.isDevOnRight
|
||
interface.io.isDevOnRightModify := slaveParser.io.isDevOnRightModify
|
||
interface.io.indexOfRightDev := slaveParser.io.indexOfRightDev
|
||
}
|
||
|
||
|
||
trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
|
||
|
||
//看门狗1~16，SM监控
|
||
val isWdtSMEnable = for( _ <- 0 until 16 ) yield { RegInit(false.B) }
|
||
val wdtSMCnt = for( _ <- 0 until 16 ) yield { RegInit(0.U(32.W)) }
|
||
|
||
for( i <- 0 until 8 ){
|
||
when( smUnit(i).io.enq ){
|
||
isWdtSMEnable(2*i) := false.B
|
||
} .elsewhen( ~isWdtSMEnable(2*i) & smUnit(i).io.sram_w.enw & interface.io.cReg.wdtEnable.extract(i+1) ){
|
||
isWdtSMEnable(2*i) := true.B
|
||
}
|
||
|
||
when( smUnit(i).io.deq ){
|
||
isWdtSMEnable(2*i + 1) := false.B
|
||
} .elsewhen( ~isWdtSMEnable(2*i + 1) & smUnit(i).io.sram_r.enr & interface.io.cReg.wdtEnable.extract(i+1) ){
|
||
isWdtSMEnable(2*i + 1) := true.B
|
||
}
|
||
}
|
||
|
||
for( i <- 0 until 16 ){
|
||
when( isWdtSMEnable(i) & (wdtSMCnt(i) < interface.io.cReg.wdtTarCnt(i+1)) ){
|
||
wdtSMCnt(i) := wdtSMCnt(i) + 1.U
|
||
} .elsewhen( ~isWdtSMEnable(i) || (wdtSMCnt(i) >= interface.io.cReg.wdtTarCnt(i+1)) ){
|
||
wdtSMCnt(i) := 0.U
|
||
}
|
||
|
||
// assert( wdtSMCnt(i) <= interface.io.cReg.wdtTarCnt(i+1), s"Assert Failed! wdtSMCnt($i) is larger than wdtTarCnt, Special situation?" )
|
||
|
||
interface.io.wdtTrigger(i+1) := wdtSMCnt(i) === interface.io.cReg.wdtTarCnt(i+1)
|
||
}
|
||
|
||
//看门狗0 发送后回包是否超时
|
||
val isWdtRec2RtnEnable = RegInit(false.B)
|
||
val wdtRec2RtnCnt = RegInit(0.U(32.W))
|
||
|
||
when(
|
||
(upCDRInAxis.io.axis.fire & upCDRInAxis.io.axis.bits.tlast) |
|
||
~interface.io.cReg.wdtEnable.extract(0)
|
||
){
|
||
isWdtRec2RtnEnable := false.B
|
||
} .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){
|
||
isWdtRec2RtnEnable := true.B
|
||
}
|
||
|
||
when( isWdtRec2RtnEnable & (wdtRec2RtnCnt < interface.io.cReg.wdtTarCnt(0)) ){
|
||
wdtRec2RtnCnt := wdtRec2RtnCnt + 1.U
|
||
} .elsewhen( ~isWdtRec2RtnEnable || (wdtRec2RtnCnt >= interface.io.cReg.wdtTarCnt(0)) ){
|
||
wdtRec2RtnCnt := 0.U
|
||
}
|
||
|
||
// assert( wdtRecCnt < interface.io.cReg.wdtTarCnt(0), "Assert Failed! wdtRecCnt is larger than wdtTarCnt, Special situation?" )
|
||
|
||
interface.io.wdtTrigger(0) := wdtRec2RtnCnt === interface.io.cReg.wdtTarCnt(0)
|
||
|
||
//看门狗17
|
||
val wdtRec2RecCnt = RegInit(0.U(32.W))
|
||
|
||
when( interface.io.cReg.wdtEnable.extract(17) & (wdtRec2RecCnt < interface.io.cReg.wdtTarCnt(17)) ){
|
||
wdtRec2RecCnt := wdtRec2RecCnt + 1.U
|
||
} .elsewhen(
|
||
~interface.io.cReg.wdtEnable.extract(17) ||
|
||
downCDRInAxis.io.axis.fire ||
|
||
(wdtRec2RecCnt >= interface.io.cReg.wdtTarCnt(17))
|
||
){
|
||
wdtRec2RecCnt := 0.U
|
||
}
|
||
|
||
interface.io.wdtTrigger(17) := wdtRec2RecCnt === interface.io.cReg.wdtTarCnt(17)
|
||
|
||
}
|
||
|
||
trait MstSlvSwitchDataPath{ this: MstSlvSwitchBase =>
|
||
val isDwUpEx = interface.io.cReg.dwupEx.extract(0)
|
||
|
||
when( ~isDwUpEx ){ //未交叉
|
||
when( interface.io.cReg.modeSel === false.B ){ //slave
|
||
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
|
||
downInSerDat := false.B
|
||
upInSerDat := false.B
|
||
when( slaveParser.io.isLoop ){ //回环
|
||
io.dDatOut := false.B
|
||
io.uDatOut := io.dDatIn
|
||
} .otherwise{ //非回环
|
||
io.dDatOut := io.dDatIn
|
||
io.uDatOut := io.uDatIn
|
||
}
|
||
} .otherwise{ //无硬件错误
|
||
when( slaveParser.io.isLoop ){ //回环
|
||
downInSerDat := io.dDatIn
|
||
upInSerDat := downCDROut.io.serDat
|
||
io.dDatOut := false.B
|
||
io.uDatOut := upCDROut.io.serDat
|
||
} .otherwise{ //非回环
|
||
downInSerDat := io.dDatIn
|
||
upInSerDat := io.uDatIn
|
||
io.dDatOut := downCDROut.io.serDat
|
||
io.uDatOut := upCDROut.io.serDat
|
||
}
|
||
}
|
||
} .otherwise{ //master
|
||
downInSerDat := false.B
|
||
upInSerDat := io.uDatIn
|
||
io.dDatOut := downCDROut.io.serDat
|
||
io.uDatOut := false.B
|
||
}
|
||
} .otherwise{ //交叉
|
||
when( interface.io.cReg.modeSel === false.B ){ //slave
|
||
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
|
||
|
||
when( slaveParser.io.isLoop ){ //回环
|
||
io.dDatOut := io.uDatIn
|
||
io.uDatOut := false.B
|
||
downInSerDat := false.B
|
||
upInSerDat := false.B
|
||
} .otherwise{ //非回环
|
||
io.dDatOut := io.dDatIn
|
||
io.uDatOut := io.uDatIn
|
||
downInSerDat := false.B
|
||
upInSerDat := false.B
|
||
}
|
||
} .otherwise{ //无硬件错误
|
||
when( slaveParser.io.isLoop ){ //回环
|
||
downInSerDat := io.uDatIn
|
||
upInSerDat := downCDROut.io.serDat
|
||
io.uDatOut := false.B
|
||
io.dDatOut := upCDROut.io.serDat
|
||
} .otherwise{ //非回环
|
||
downInSerDat := io.uDatIn
|
||
upInSerDat := io.dDatIn
|
||
io.dDatOut := upCDROut.io.serDat
|
||
io.uDatOut := downCDROut.io.serDat
|
||
}
|
||
}
|
||
} .otherwise{ //master
|
||
downInSerDat := false.B
|
||
upInSerDat := io.dDatIn
|
||
io.uDatOut := downCDROut.io.serDat
|
||
io.dDatOut := false.B
|
||
}
|
||
}
|
||
}
|
||
|
||
trait MstSlvSwitchB8B4{ this: MstSlvSwitchBase =>
|
||
val isUsing8b10b = interface.io.cReg.b8b4Sel.extract(0)
|
||
|
||
when( isUsing8b10b ){
|
||
b8b10DownEncoder.io <> downCDROut.io.encode
|
||
b8b10DownDecoder.io <> downCDRInAxis.io.decode
|
||
b8b10UpEncoder.io <> upCDROut.io.encode
|
||
b8b10UpDecoder.io <> upCDRInAxis.io.decode
|
||
|
||
b4b5DownEncoder.io.isEnable := false.B
|
||
b4b5DownEncoder.io.dataIn := 0.U
|
||
b4b5DownDecoder.io.dataIn := 0.U
|
||
b4b5UpEncoder.io.isEnable := false.B
|
||
b4b5UpEncoder.io.dataIn := 0.U
|
||
b4b5UpDecoder.io.dataIn := 0.U
|
||
} .otherwise{
|
||
b4b5DownEncoder.io <> downCDROut.io.encode
|
||
b4b5DownDecoder.io <> downCDRInAxis.io.decode
|
||
b4b5UpEncoder.io <> upCDROut.io.encode
|
||
b4b5UpDecoder.io <> upCDRInAxis.io.decode
|
||
|
||
b8b10DownEncoder.io.isEnable := false.B
|
||
b8b10DownEncoder.io.dataIn := 0.U
|
||
b8b10DownDecoder.io.dataIn := 0.U
|
||
b8b10UpEncoder.io.isEnable := false.B
|
||
b8b10UpEncoder.io.dataIn := 0.U
|
||
b8b10UpDecoder.io.dataIn := 0.U
|
||
}
|
||
}
|
||
|
||
trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase =>
|
||
val cdrSelB = interface.io.cReg.cdrParam === 1.U
|
||
val cdrSelC = interface.io.cReg.cdrParam === 2.U
|
||
val cdrSelA = ~cdrSelB & ~cdrSelC
|
||
|
||
when(cdrSelB){
|
||
io.downCDRSampleIn(1).serDat := downInSerDat
|
||
io.upCDRSampleIn(1).serDat := upInSerDat
|
||
downInSyncSerDat := io.downCDRSampleIn(1).syncSerDat
|
||
upInSyncSerDat := io.upCDRSampleIn(1).syncSerDat
|
||
|
||
io.downCDRSampleIn(0).serDat := false.B
|
||
io.upCDRSampleIn(0).serDat := false.B
|
||
io.downCDRSampleIn(2).serDat := false.B
|
||
io.upCDRSampleIn(2).serDat := false.B
|
||
} .elsewhen(cdrSelC){
|
||
io.downCDRSampleIn(2).serDat := downInSerDat
|
||
io.upCDRSampleIn(2).serDat := upInSerDat
|
||
downInSyncSerDat := io.downCDRSampleIn(2).syncSerDat
|
||
upInSyncSerDat := io.upCDRSampleIn(2).syncSerDat
|
||
|
||
io.downCDRSampleIn(0).serDat := false.B
|
||
io.upCDRSampleIn(0).serDat := false.B
|
||
io.downCDRSampleIn(1).serDat := false.B
|
||
io.upCDRSampleIn(1).serDat := false.B
|
||
} .otherwise{
|
||
io.downCDRSampleIn(0).serDat := downInSerDat
|
||
io.upCDRSampleIn(0).serDat := upInSerDat
|
||
downInSyncSerDat := io.downCDRSampleIn(0).syncSerDat
|
||
upInSyncSerDat := io.upCDRSampleIn(0).syncSerDat
|
||
|
||
io.downCDRSampleIn(1).serDat := false.B
|
||
io.upCDRSampleIn(1).serDat := false.B
|
||
io.downCDRSampleIn(2).serDat := false.B
|
||
io.upCDRSampleIn(2).serDat := false.B
|
||
}
|
||
|
||
|
||
|
||
}
|
||
|
||
class MstSlvSwitch extends MstSlvSwitchBase
|
||
with MstSlvSwitchMaster
|
||
with MstSlvSwitchSlave
|
||
with MstSlvSwitchWatchDog
|
||
with MstSlvSwitchDataPath
|
||
with MstSlvSwitchB8B4
|
||
with MstSlvSwitchCDRIn{
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
}
|