350 lines
10 KiB
Scala
350 lines
10 KiB
Scala
package Switch
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import chisel3._
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import chisel3.util._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tilelink._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.interrupts._
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class Mac_Config_Bundle extends Bundle{
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val WCtrlDataStart = Input(Bool())
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val RStatStart = Input(Bool())
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val UpdateMIIRX_DATAReg = Input(Bool())
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val Prsd = Input(UInt(16.W))
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val NValid_stat = Input(Bool())
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val Busy_stat = Input(Bool())
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val LinkFail = Input(Bool())
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val TxB_IRQ = Input(Bool())
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val TxE_IRQ = Input(Bool())
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val RxB_IRQ = Input(Bool())
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val RxE_IRQ = Input(Bool())
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val Busy_IRQ = Input(Bool())
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val StartTxDone = Input(Bool())
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val TxClk = Input(Bool())
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val RxClk = Input(Bool())
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val r_FullD = Output(Bool())
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val r_ExDfrEn = Output(Bool())
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val r_LoopBck = Output(Bool())
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val r_IFG = Output(Bool())
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val r_NoPre = Output(Bool())
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val r_TxEn = Output(Bool())
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val r_RxEn = Output(Bool())
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val r_HASH0 = Output(UInt(32.W))
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val r_HASH1 = Output(UInt(32.W))
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val r_IPGT = Output(UInt(7.W))
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val r_IPGR1 = Output(UInt(7.W))
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val r_IPGR2 = Output(UInt(7.W))
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val r_CollValid = Output(UInt(6.W))
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val r_MiiNoPre = Output(Bool())
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val r_ClkDiv = Output(UInt(8.W))
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val r_WCtrlData = Output(Bool())
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val r_RStat = Output(Bool())
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val r_ScanStat = Output(Bool())
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val r_RGAD = Output(UInt(5.W))
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val r_FIAD = Output(UInt(5.W))
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val r_CtrlData = Output(UInt(16.W))
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}
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class MacRegIO extends Mac_Config_Bundle{
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val asyncReset = Input(AsyncReset())
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}
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class MacReg(chn: Int)(implicit p: Parameters) extends LazyModule{
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// DTS
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val dtsdevice = new SimpleDevice(s"mac($chn)",Seq(s"mac_($chn)"))
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val int_node = IntSourceNode(IntSourcePortSimple(num = 1, resources = dtsdevice.int))
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val configNode = TLRegisterNode(
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address = Seq(AddressSet(0x30000000L + 0x100*chn, 0x000000ffL)),
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device = dtsdevice,
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concurrency = 1,
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beatBytes = 32/8,
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executable = true
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)
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lazy val module = new MacRegImp(this)
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}
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class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(outer) with HasSwitchParameters{
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val io: MacRegIO = IO(new MacRegIO)
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val (int, _) = outer.int_node.out(0)
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val FullD = RegInit(false.B)
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val ExDfrEn = RegInit(false.B)
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val LoopBck = RegInit(false.B)
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val IFG = RegInit(false.B)
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val NoPre = RegInit(false.B)
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val TxEn = RegInit(false.B)
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val RxEn = RegInit(false.B)
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// Interrupt generation
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val irq_txb = RegInit(false.B)
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val irq_txe = RegInit(false.B)
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val irq_rxb = RegInit(false.B)
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val irq_rxe = RegInit(false.B)
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val irq_busy = RegInit(false.B)
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val INT_MASK = RegInit(0.U(7.W)) // INT_MASK Register
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val IPGT = RegInit("h12".U(7.W)) // IPGT Register
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val IPGR1 = RegInit("h0C".U(7.W)) // IPGR1 Register
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val IPGR2 = RegInit("h12".U(7.W))
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val collValid = RegInit("h3f".U(6.W))
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val clkDiv = RegInit("h64".U(8.W))
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val miiNoPre = RegInit(false.B)
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val scanStat = RegInit(false.B)
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val readStat = RegInit(false.B)
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val wCtrlData = RegInit(false.B)
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when(io.RStatStart){ readStat := false.B }
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when(io.WCtrlDataStart){ wCtrlData := false.B }
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val FIAD = RegInit(0.U(5.W))
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val RGAD = RegInit(0.U(5.W))
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val MIITX_DATA = RegInit(0.U(16.W)) // MIITX_DATA Register
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val MIIRX_DATA = RegEnable(io.Prsd, 0.U(16.W), io.UpdateMIIRX_DATAReg) // MIIRX_DATA Register
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val HASH0 = RegInit(0.U(32.W))
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val HASH1 = RegInit(0.U(32.W))
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outer.configNode.regmap(
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( 0 << 2 ) ->
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RegFieldGroup("MODER", Some("Mode Register"), Seq(
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RegField(1, RxEn , RegFieldDesc( "RxEn", "RxEn", reset = Some(0))) ,
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RegField(1, TxEn , RegFieldDesc( "TxEn", "TxEn", reset = Some(0) ) ),
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RegField(1, NoPre , RegFieldDesc( "NoPre", "NoPre", reset = Some(0) ) ),
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RegField.r(1, 0.U , RegFieldDesc( "Bro", "Bro", reset = Some(0) ) ),
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RegField.r(1, 0.U , RegFieldDesc( "Iam", "Iam Unused", reset = Some(0) ) ),
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RegField.r(1, 0.U , RegFieldDesc( "Pro", "Pro", reset = Some(0) ) ),
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RegField(1, IFG , RegFieldDesc( "IFG", "IFG", reset = Some(0) ) ),
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RegField(1, LoopBck, RegFieldDesc( "LoopBck", "LoopBck", reset = Some(0) ) ),
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RegField.r(1, 0.U, RegFieldDesc( "NoBckof", "NoBckof", reset = Some(0) ) ),
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RegField(1, ExDfrEn, RegFieldDesc( "ExDfrEn", "ExDfrEn", reset = Some(0) ) ),
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RegField(1, FullD , RegFieldDesc( "FullD", "FullD", reset = Some(0) ) ),
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RegField.r(1, 0.U),
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RegField.r(1, 0.U, RegFieldDesc( "DlyCrcEn", "DlyCrcEn", reset=Some(0)) ),
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RegField.r(1, 0.U, RegFieldDesc( "CrcEn", "CrcEn", reset=Some(1)) ),
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RegField.r(1, 1.U , RegFieldDesc( "HugEn", "HugEn", reset=Some(0)) ),
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RegField.r(1, 1.U , RegFieldDesc( "Pad", "Pad", reset=Some(1)) ),
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RegField.r(1, 1.U, RegFieldDesc( "RecSmall", "RecSmall", reset=Some(0)) )
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)),
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( 1 << 2 ) ->
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RegFieldGroup("INT_SOURCE", Some("Interrupt Source Register"), Seq(
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RegField(1, irq_txb, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_txb := 0.U }; true.B }), RegFieldDesc("txb", "txb", reset=Some(0))),
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RegField(1, irq_txe, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_txe := 0.U }; true.B }), RegFieldDesc("txe", "txe", reset=Some(0))),
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RegField(1, irq_rxb, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_rxb := 0.U }; true.B }), RegFieldDesc("rxb", "rxb", reset=Some(0))),
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RegField(1, irq_rxe, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_rxe := 0.U }; true.B }), RegFieldDesc("rxe", "rxe", reset=Some(0))),
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RegField(1, irq_busy, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_busy := 0.U }; true.B }), RegFieldDesc("busy", "busy", reset=Some(0))),
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RegField.r(1, 0.U, RegFieldDesc("txc", "txc", reset=Some(0))),
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RegField.r(1, 0.U, RegFieldDesc("rxc", "rxc", reset=Some(0))),
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)),
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( 2 << 2 ) ->
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RegFieldGroup("INT_MASK", Some("Interrupt Mask Register"), Seq(
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RegField(7, INT_MASK)
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)),
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( 3 << 2 ) ->
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RegFieldGroup("IPGT", Some("Back to Back Inter Packet Gap Register"), Seq(
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RegField(7, IPGT, RegFieldDesc("IPGT", "IPGT", reset=Some(0x12)))
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)),
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( 4 << 2 ) ->
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RegFieldGroup("IPGR1", Some("Non Back to Back Inter Packet Gap Register 1"), Seq(
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RegField(7, IPGR1, RegFieldDesc("IPGR1", "IPGR1", reset=Some(0xc)))
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)),
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( 5 << 2 ) ->
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RegFieldGroup("IPGR2", Some("Non Back to Back Inter Packet Gap Register 2"), Seq(
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RegField(7, IPGR2, RegFieldDesc("IPGR2", "IPGR2", reset=Some(0x12)))
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)),
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( 7 << 2 ) ->
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RegFieldGroup("COLLCONF", Some("Collision and Retry Configuration Register"), Seq(
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RegField(6, collValid, RegFieldDesc("collValid", "Collision Valid", reset=Some(0x3f))),
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RegField.r(10,0.U),
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RegField.r(4, 0.U, RegFieldDesc("maxRet", "Maximum Retry", reset=Some(0xf))),
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)),
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( 10 << 2 ) ->
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RegFieldGroup("MIIMODER", Some("MII Mode Register"), Seq(
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RegField(8, clkDiv, RegFieldDesc("clkDiv", "Clock Divider", reset=Some(0x64))),
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RegField(1, miiNoPre, RegFieldDesc("MIINoPre", "NO Preamble", reset=Some(0x0))),
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)),
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( 11 << 2 ) ->
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RegFieldGroup("MIICOMMAND", Some("MII Command Register"), Seq(
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RegField(1, scanStat, RegFieldDesc("scanStat", "Scan Status", reset=Some(0x0))),
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RegField(1, readStat, RegFieldDesc("readStat", "Read Status", reset=Some(0x0))),
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RegField(1, wCtrlData, RegFieldDesc("wCtrlData", "Write Control Data", reset=Some(0x0))),
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)),
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( 12 << 2 ) ->
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RegFieldGroup("MIIADDRESS", Some("MII Address Register"), Seq(
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RegField(5, FIAD, RegFieldDesc("FIAD", "PHY Address", reset=Some(0x0))),
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RegField.r(3 ,0.U),
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RegField(5, RGAD, RegFieldDesc("RGAD", "Register Address", reset=Some(0x0))),
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)),
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( 13 << 2 ) ->
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RegFieldGroup("MIITX_DATA", Some("MII Transmit Data"),
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RegField.bytes(MIITX_DATA)
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),
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( 14 << 2 ) ->
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RegFieldGroup("MIIRX_DATA", Some("MII Receive Data"), Seq(
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RegField.r(16, MIIRX_DATA)
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)),
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( 15 << 2 ) ->
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RegFieldGroup("MIISTATUS", Some("MII Status Register"), Seq(
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RegField.r(1, io.LinkFail),
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RegField.r(1, io.Busy_stat),
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RegField.r(1, io.NValid_stat),
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)),
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( 16 << 2 ) ->
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RegFieldGroup("MAC_ADDR0", Some("MAC Address Register 0"), Seq(
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RegField(32)
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)),
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( 17 << 2 ) ->
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RegFieldGroup("MAC_ADDR1", Some("MAC Address Register 1"), Seq(
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RegField(32)
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)),
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( 18 << 2 ) ->
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RegFieldGroup("HASH0", Some("HASH Register 0"),
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RegField.bytes(HASH0)
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),
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( 19 << 2 ) ->
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RegFieldGroup("HASH1", Some("HASH Register 1"),
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RegField.bytes(HASH1)
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),
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)
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io.r_FullD := FullD
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io.r_ExDfrEn := ExDfrEn
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io.r_LoopBck := LoopBck
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io.r_IFG := IFG
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io.r_NoPre := NoPre
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io.r_TxEn := TxEn
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io.r_RxEn := RxEn
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io.r_IPGT := IPGT
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io.r_IPGR1 := IPGR1
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io.r_IPGR2 := IPGR2
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io.r_CollValid := collValid
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io.r_MiiNoPre := miiNoPre
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io.r_ClkDiv := clkDiv
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io.r_WCtrlData := wCtrlData
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io.r_RStat := readStat
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io.r_ScanStat := scanStat
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io.r_RGAD := RGAD
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io.r_FIAD := FIAD
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io.r_CtrlData := MIITX_DATA
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io.r_HASH1 := HASH1
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io.r_HASH0 := HASH0
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when(io.TxB_IRQ){ irq_txb := true.B }
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when(io.TxE_IRQ){ irq_txe := true.B }
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when(io.RxB_IRQ){ irq_rxb := true.B }
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when(io.RxE_IRQ){ irq_rxe := true.B }
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when(io.Busy_IRQ){ irq_busy := true.B }
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// Generating interrupt signal
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// io.int_o :=
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int(0) :=
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(irq_txb & INT_MASK.extract(0) ) |
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(irq_txe & INT_MASK.extract(1) ) |
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(irq_rxb & INT_MASK.extract(2) ) |
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(irq_rxe & INT_MASK.extract(3) ) |
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(irq_busy & INT_MASK.extract(4) )
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}
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