104 lines
2.1 KiB
Scala
104 lines
2.1 KiB
Scala
package Switch
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import chisel3._
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import chisel3.util._
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import MAC._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import chisel3.experimental.dataview._
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class SwitchIO(implicit p: Parameters) extends SwitchBundle{
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val mii = Vec( chn, new MII )
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val isLoopBack = Output(Vec( chn, Bool()))
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val asyncReset = Input(AsyncReset())
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}
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class Switch(implicit p: Parameters) extends LazyModule with HasSwitchParameters{
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val tlClientNode = TLClientNode(Seq(TLMasterPortParameters.v1(
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Seq(TLMasterParameters.v1(
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name = "DMA",
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sourceId = IdRange(0, chn),
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))
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)))
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val ethReg = LazyModule(new MacReg)
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lazy val module = new SwitchImp(this)
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}
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class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(outer) with HasSwitchParameters{
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val io = IO(new SwitchIO)
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val ( dma_bus, dma_edge ) = outer.tlClientNode.out.head
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val mac = ( 0 until chn ).map{ i =>
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Module(new Mac)
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}
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( 0 until chn ).map{ i =>
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mac(i).io.mii <> io.mii(i)
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mac(i).io.asyncReset := io.asyncReset
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io.isLoopBack(i) := mac(i).io.isLoopBack
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}
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outer.ethReg.module.io.asyncReset := io.asyncReset
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outer.ethReg.module.io.viewAsSupertype(new Mac_Config_Bundle) <> mac(0).io.cfg
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val dmaMst = Module(new DMAMst(dma_edge))
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dmaMst.io.rxEnq(0) <> mac(0).io.rxEnq
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dmaMst.io.txDeq(0) <> mac(0).io.txDeq
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dmaMst.io.triTx := outer.ethReg.module.io.triTx
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outer.ethReg.module.io.triRx := dmaMst.io.triRx
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dmaMst.io.r_TxPtr := outer.ethReg.module.io.r_TxPtr
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dmaMst.io.r_RxPtr := outer.ethReg.module.io.r_RxPtr
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dmaMst.io.r_TxLen := outer.ethReg.module.io.r_TxLen
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outer.ethReg.module.io.r_RxLen := dmaMst.io.r_RxLen
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dmaMst.io.dmaMst.D.bits := dma_bus.d.bits
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dmaMst.io.dmaMst.D.valid := dma_bus.d.valid
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dma_bus.d.ready := dmaMst.io.dmaMst.D.ready
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dma_bus.a.valid := dmaMst.io.dmaMst.A.valid
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dma_bus.a.bits := dmaMst.io.dmaMst.A.bits
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dmaMst.io.dmaMst.A.ready := dma_bus.a.ready
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}
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