54 lines
1.2 KiB
Scala
54 lines
1.2 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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import chisel3.experimental._
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class picorv32 extends BlackBox() with HasBlackBoxResource {
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val io = IO(new Bundle {
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val clk = Input(Bool())
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val resetn = Input(Bool())
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val trap = Output(Bool())
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val mem_valid = Output(Bool())
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val mem_instr = Output(Bool())
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val mem_ready = Input(Bool())
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val mem_addr = Output(UInt(32.W))
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val mem_wdata = Output(UInt(32.W))
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val mem_wstrb = Output(UInt(4.W))
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val mem_rdata = Input(UInt(32.W))
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// Look-Ahead Interface
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val mem_la_read = Output(Bool())
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val mem_la_write = Output(Bool())
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val mem_la_addr = Output(UInt(32.W))
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val mem_la_wdata = Output(UInt(32.W))
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val mem_la_wstrb = Output(UInt(4.W))
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// Pico Co-Processor Interface (PCPI)
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val pcpi_valid = Output(Bool())
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val pcpi_insn = Output(UInt(32.W))
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val pcpi_rs1 = Output(UInt(32.W))
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val pcpi_rs2 = Output(UInt(32.W))
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val pcpi_wr = Input(Bool())
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val pcpi_rd = Input(UInt(32.W))
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val pcpi_wait = Input(Bool())
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val pcpi_ready = Input(Bool())
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// IRQ Interface
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val irq = Input(UInt(32.W))
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val eoi = Output(UInt(32.W))
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// Trace Interface
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val trace_valid = Output(Bool())
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val trace_data = Output(UInt(36.W))
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})
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addResource("./picorv32.v")
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}
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