87 lines
1.9 KiB
Scala
87 lines
1.9 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class LVDS_SLV_Bundle extends Bundle{
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val downstream_rx_data_valid = Input(Bool())
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val downstream_rx_data_out = Input(UInt(8.W))
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val downstream_rx_crc_valid = Input(Bool())
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val downstream_rx_crc_err = Input(Bool())
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val upstream_tx_data_in = Output(UInt(8.W))
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val upstream_tx_data_ready = Input(Bool())
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val downstream_rx_cdr_err = Input(Bool())
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val upstream_rx_cdr_err = Input(Bool())
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}
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class BackBoardSlvIO extends Bundle{
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val isOnline = Output(Bool())
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val isLast = Input(Bool())
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val DCIn = Input(Bool())
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val lvdsSlv = new LVDS_SLV_Bundle
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}
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abstract class BackBoardSlvBase extends Module{
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val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
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val downRegTemp = RegInit(VecInit( Seq(15.U(8.W)) ++ Seq.fill(31){0.U(8.W)} ))
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val upReg = WireDefault(VecInit((0 until 32).map{i => 0.U(8.W)}))
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}
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trait BackBoardSlvDown{ this: BackBoardSlvBase =>
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val downCnt = Reg(UInt(6.W))
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when( io.lvdsSlv.downstream_rx_data_valid ){
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downRegTemp(downCnt) := io.lvdsSlv.downstream_rx_data_out
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downCnt := downCnt + 1.U
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} .otherwise{
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downCnt := 0.U
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}
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val isCrcPass = io.lvdsSlv.downstream_rx_crc_valid & ~io.lvdsSlv.downstream_rx_crc_err
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// when( io.lvdsSlv.downstream_rx_crc_valid ){
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// when( ~io.lvdsSlv.downstream_rx_crc_err ){
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// for( i <- 1 until 32 ) {
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// downReg(i) := downRegTemp(i)
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// }
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// }
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// }
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// when( RegNext(io.lvdsSlv.downstream_rx_data_valid,false.B) & ~io.lvdsSlv.downstream_rx_data_valid ){
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// for( i <- 1 until 32 ) {
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// downReg(i) := downRegTemp(i)
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// }
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// }
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}
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trait BackBoardSlvUp{ this: BackBoardSlvBase =>
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val upCnt = Reg(UInt(6.W))
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io.lvdsSlv.upstream_tx_data_in := upReg(upCnt)
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when( io.lvdsSlv.upstream_tx_data_ready ){
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when( ~RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) ){
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upCnt := 0.U
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} .otherwise{
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upCnt := upCnt + 1.U
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}
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}
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}
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