106 lines
3.4 KiB
Scala
106 lines
3.4 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class BackBoardSlvIO extends Bundle{
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val localHost = Input(UInt(5.W))
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val upStreamReqDat = Input( Bool() )
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val downStreamReqDat = Input( Bool() )
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val upStreamRespdat = Output(Bool())
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val downStreamRespdat = Output(Bool())
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val clk4 = Input( Bool() )
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}
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abstract class BackBoardSlvBase extends Module{
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val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
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val upStreamReq = Module(new CDR4MultiIn)
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val downStreamReq = Module(new CDR4MultiIn)
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val upStreamResp = Module(new CDROutBus)
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val downStreamResp = Module(new CDROutBus)
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upStreamReq.io.clk4 := io.clk4
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downStreamReq.io.clk4 := io.clk4
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upStreamReq.io.dat := io.upStreamReqDat
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downStreamReq.io.dat := io.downStreamReqDat
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io.upStreamRespdat := upStreamResp.io.dat
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io.downStreamRespdat := downStreamResp.io.dat
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def IDLE = 0.U
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def UPSTREAM_RESP = 1.U
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def DOWNSTREAM_RESP = 2.U
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val stateNext = Wire( UInt(2.W) )
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val stateCurr = RegNext(stateNext, 0.U)
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stateNext := Mux1H(Seq(
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(stateCurr === IDLE) -> Mux(upStreamReq.io.latDat.fire, Mux(upStreamReq.io.latDat.bits.address(5,1) === io.localHost, UPSTREAM_RESP, DOWNSTREAM_RESP), Mux(downStreamReq.io.latDat.fire, UPSTREAM_RESP, IDLE) ),
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(stateCurr === UPSTREAM_RESP) -> Mux(upStreamResp.io.pkgDat.fire, IDLE, UPSTREAM_RESP ),
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(stateCurr === DOWNSTREAM_RESP) -> Mux(downStreamResp.io.pkgDat.fire, IDLE, DOWNSTREAM_RESP ),
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))
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val upStreamReqReady = RegInit(false.B); upStreamReq.io.latDat.ready := upStreamReqReady
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val downStreamReqReady = RegInit(false.B); downStreamReq.io.latDat.ready := downStreamReqReady
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val upStreamRespValid = RegInit(false.B); upStreamResp.io.pkgDat.valid := upStreamRespValid
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val upStreamRespInfo = Reg(new CDRData); upStreamResp.io.pkgDat.bits := upStreamRespInfo
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val downStreamRespValid = RegInit(false.B); downStreamResp.io.pkgDat.valid := downStreamRespValid
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val downStreamRespInfo = Reg(new CDRData); downStreamResp.io.pkgDat.bits := downStreamRespInfo
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val registersRD = Wire(UInt(32.W))
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}
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trait StatusControl{ this: BackBoardSlvBase =>
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when( upStreamResp.io.pkgDat.fire ){
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upStreamRespValid := false.B
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} .elsewhen( downStreamResp.io.pkgDat.fire ){
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downStreamRespValid := false.B
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}.elsewhen( upStreamReq.io.latDat.fire ){
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upStreamReqReady := false.B
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when( upStreamReq.io.latDat.bits.address(5,1) === io.localHost ){
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upStreamRespValid := true.B
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upStreamRespInfo.address := upStreamReq.io.latDat.bits.address
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upStreamRespInfo.register := upStreamReq.io.latDat.bits.register
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upStreamRespInfo.data := Mux(upStreamReq.io.latDat.bits.address.extract(0) === 0.U, registersRD, 0.U )
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upStreamRespInfo.hash := 0.U
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} .otherwise{
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downStreamRespValid := true.B
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downStreamRespInfo := upStreamReq.io.latDat.bits
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}
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} .elsewhen( downStreamReq.io.latDat.fire ){
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downStreamReqReady := false.B
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upStreamRespValid := true.B
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upStreamRespInfo := downStreamReq.io.latDat.bits
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} .elsewhen( downStreamReq.io.latDat.valid & ~downStreamReq.io.latDat.ready && stateCurr === IDLE ){
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downStreamReqReady := true.B
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} .elsewhen( upStreamReq.io.latDat.valid & ~upStreamReq.io.latDat.ready & ~downStreamReq.io.latDat.valid & stateCurr === IDLE ){
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upStreamReqReady := true.B
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}
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}
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class BackBoardSlv extends BackBoardSlvBase with StatusControl with LocalRegisters
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