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eb001/tb/sw/src/mstSvr.S

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#include "tl2cdr.h"
#include "sysDef.h"
#if 0
/*
使RV32E RV32I 使x0, x16~x31
便使ABI使x0, x16~x31x1~x15使ABI
x16~x23, 使
x24, TL2CDR_BASE
x25, 4
x26, 4(tx0_txLen)
x27,
x28, plic_claim
x29, REG_ISR_ADDR
x30,
x31,
*/
#endif
#define REG_TL2CDR_BASE x24
#define REG_rx_data x25
#define REG_tx_data x26
#define REG_tx_data_len x27
#define REG_plic_claim x28
#define REG_ISR_ADDR x29
#define REG_min_isr_num x30
#define REG_max_isr_num x31
.globl _prog_start
.globl _rv32i_plic_handle
.section .text.init, "ax", %progbits
_prog_start:
//a0 call_function no
li x16, SYS_INIT
beqz a0, init_system_func //
li x16, SYS_SEND_DATA
beq a0, x16, send_data_func
li x16, SYS_SET_RECV_INFO
beq a0, x16, set_recv_info_func
10: j 10b //
ret //
//
//a1, plic_claim,
init_system_func:
mv REG_plic_claim, a1 # plic_claim
/*初始化isr_hdl_table中断表*/
la x16, isr_hdl_table
la x17, isr_tx0_end_hdl
addi x16, x16, 4
sw x17, 0(x16)
la x17, isr_tx1_end_hdl
addi x16, x16, 4
sw x17, 0(x16)
la x17, isr_rx0_err_hdl
addi x16, x16, 4
sw x17, 0(x16)
la x17, isr_rx1_err_hdl
addi x16, x16, 4
sw x17, 0(x16)
la x17, isr_rx0_start_hdl
addi x16, x16, 4
sw x17, 0(x16)
la x17, isr_rx1_start_hdl
addi x16, x16, 4
sw x17, 0(x16)
la x17, isr_rx0_end_hdl
addi x16, x16, 4
sw x17, 0(x16)
la x17, isr_rx1_end_hdl
addi x16, x16, 4
sw x17, 0(x16)
la x17, isr_tx0_deq_hdl
addi x16, x16, 4
sw x17, 0(x16)
la x17, isr_tx1_deq_hdl
addi x16, x16, 4
sw x17, 0(x16)
la x17, isr_rx0_enq_hdl
addi x16, x16, 4
sw x17, 0(x16)
la x17, isr_rx1_enq_hdl
addi x16, x16, 4
sw x17, 0(x16)
la x17, _rv32i_plic_handle
mv a0, x17
li REG_TL2CDR_BASE, TL2CDR_BASE
la REG_ISR_ADDR, isr_hdl_table
li REG_min_isr_num, 14
li REG_max_isr_num, 25
li x23, 4
ret
//
//a1,
//a2,
send_data_func:
mv REG_tx_data, a1
mv REG_tx_data_len, a2
//*tx0_txLen = 8 + tx_len; //前导+长度命令
mv x16, a2
addi x17, x16, 8
sw x17, TX0_WriteTxLen(REG_TL2CDR_BASE)
//*tx0_txFifo = (tx_len << 20) | (0 << 16) | 0x0000;
slli x17, x16, 20
sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
//*tx0_txFifo = data[0]
lw x17, 0(REG_tx_data)
sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
//li x16, 4
add REG_tx_data, REG_tx_data, x23
sub REG_tx_data_len, REG_tx_data_len, x23
li a0, 1
ret
//,
//a1,
set_recv_info_func:
mv REG_rx_data, a1
li a0, 1
ret
//--------------------------------------------
//
.balign 32
_rv32i_plic_handle:
lw x16, 0(REG_plic_claim) # x16 = *plic_claim
sw x16, 0(REG_plic_claim) # *plic_claim = x16
bltu x16, REG_min_isr_num, exit_handle #if x16 < REG_min_isr_num then goto exit_handle
bltu REG_max_isr_num, x16, exit_handle #if REG_max_isr_num < x16 then goto exit_handle
sub x17, x16, REG_min_isr_num
slli x17, x17, 2 # x17 = x17 * 4
add x18, REG_ISR_ADDR, x17 # x18 = REG_ISR_ADDR + x17
jr x18
exit_handle:
mret
isr_tx0_end_hdl:
mret
isr_tx1_end_hdl:
mret
isr_rx0_err_hdl:
mret
isr_rx1_err_hdl:
mret
isr_rx0_start_hdl:
mret
isr_rx1_start_hdl:
lw x22, RX1_ReadRxLen(REG_TL2CDR_BASE)
sw x22, 0(REG_rx_data)
add REG_rx_data, REG_rx_data, x23
mret
isr_rx0_end_hdl:
mret
isr_rx1_end_hdl:
mret
isr_tx0_deq_hdl:
bgtz REG_tx_data_len, 1f //if (REG_tx_data_len > 0)
lw x17, 0(REG_tx_data)
sw x17, TX0_WriteTxFifo(REG_TL2CDR_BASE)
//li x16, 4
add REG_tx_data, REG_tx_data, x23
sub REG_tx_data_len, REG_tx_data_len, x23
1:
mret
isr_tx1_deq_hdl:
mret
isr_rx0_enq_hdl:
lw x17, RX1_ReadRxFifo(REG_TL2CDR_BASE)
sw x17, 0(REG_rx_data)
add REG_rx_data, REG_rx_data, x23
mret
isr_rx1_enq_hdl:
mret
.balign 4
isr_hdl_table:
.space 64
nop