126 lines
3.9 KiB
Scala
126 lines
3.9 KiB
Scala
package MAC
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import chisel3._
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import chisel3.util._
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class MacTileLinkTxIO extends Bundle{
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val RstDeferLatched = Output(Bool())
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val BlockingTxStatusWrite_sync = Input(Bool())
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val TxStartFrm_sync = Input(Bool())
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val TxStartFrm = Output(Bool()) // Transmit packet start frame
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val TxEndFrm = Output(Bool()) // Transmit packet end frame
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val TxData = Output(UInt(8.W)) // Transmit packet data byte
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val TxUsedData = Input(Bool()) // Transmit packet used data
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val TxRetry = Input(Bool()) // Transmit packet retry
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val TxAbort = Input(Bool()) // Transmit packet abort
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val TxDone = Input(Bool()) // Transmission ended
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val ReadTxDataFromFifo_tck = Output(Bool())
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val ReadTxDataFromFifo_syncb = Input(Bool())
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val TxEndFrm_wb = Input(Bool())
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val TxValidBytesLatched = Input(UInt(2.W))
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val TxData_wb = Input(UInt(32.W))
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}
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class MacTileLinkTx extends Module with RequireAsyncReset{
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val io = IO(new MacTileLinkTxIO)
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io.RstDeferLatched := io.BlockingTxStatusWrite_sync & ~RegNext(io.BlockingTxStatusWrite_sync, false.B)
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val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm
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val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm
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val TxData = RegInit(0.U(8.W)); io.TxData := TxData
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val TxDataLatched = RegInit(0.U(32.W))
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val TxByteCnt = RegInit(0.U(2.W))
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val LastWord = RegInit(false.B)
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val ReadTxDataFromFifo_tck = RegInit(false.B); io.ReadTxDataFromFifo_tck := ReadTxDataFromFifo_tck
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// Generating delayed signals
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val TxAbort_q = RegNext( io.TxAbort, false.B)
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val TxRetry_q = RegNext( io.TxRetry, false.B)
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val TxUsedData_q = RegNext( io.TxUsedData, false.B)
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// Changes for tx occur every second clock. Flop is used for this manner.
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val Flop = RegInit(false.B)
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when( io.TxDone | io.TxAbort | TxRetry_q){
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Flop := false.B
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} .elsewhen ( io.TxUsedData ){
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Flop := ~Flop
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}
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when(io.TxStartFrm_sync){
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TxStartFrm := true.B
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} .elsewhen(TxUsedData_q | ~io.TxStartFrm_sync & (io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q))){
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TxStartFrm := false.B
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}
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// Indication of the last word
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when( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){
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LastWord := false.B
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} .elsewhen( io.TxUsedData & Flop & TxByteCnt === 3.U ){
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LastWord := io.TxEndFrm_wb
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}
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// Tx end frame generation
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when(Flop & TxEndFrm | io.TxAbort | TxRetry_q){
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TxEndFrm := false.B
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} .elsewhen(Flop & LastWord){
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TxEndFrm :=
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Mux1H(Seq(
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(io.TxValidBytesLatched === 1.U) -> (TxByteCnt === 0.U),
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(io.TxValidBytesLatched === 2.U) -> (TxByteCnt === 1.U),
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(io.TxValidBytesLatched === 3.U) -> (TxByteCnt === 2.U),
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(io.TxValidBytesLatched === 0.U) -> (TxByteCnt === 3.U),
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))
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}
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// Tx data selection (latching)
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when( io.TxStartFrm_sync & ~TxStartFrm ){
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TxData := io.TxData_wb( 7, 0) // little Endian Byte Ordering
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} .elsewhen(io.TxUsedData & Flop){
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TxData := Mux1H(Seq(
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(TxByteCnt === 0.U) -> TxDataLatched( 7, 0),// little Endian Byte Ordering
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(TxByteCnt === 1.U) -> TxDataLatched(15, 8),
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(TxByteCnt === 2.U) -> TxDataLatched(23,16),
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(TxByteCnt === 3.U) -> TxDataLatched(31,24),
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))
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}
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// Latching tx data
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when(
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io.TxStartFrm_sync & ~TxStartFrm |
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io.TxUsedData & Flop & TxByteCnt === 3.U |
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TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U){
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TxDataLatched := io.TxData_wb
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}
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// Tx Byte counter
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when(TxAbort_q | TxRetry_q){
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TxByteCnt := 0.U
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} .elsewhen(TxStartFrm & ~io.TxUsedData){
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TxByteCnt := 1.U
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} .elsewhen(io.TxUsedData & Flop){
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TxByteCnt := TxByteCnt + 1.U
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}
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when(
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io.TxStartFrm_sync & ~TxStartFrm |
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io.TxUsedData & Flop & TxByteCnt === 3.U & ~LastWord |
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TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){
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ReadTxDataFromFifo_tck := true.B
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} .elsewhen(io.ReadTxDataFromFifo_syncb & ~RegNext(io.ReadTxDataFromFifo_syncb, false.B)){
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ReadTxDataFromFifo_tck := false.B
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}
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}
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