36 lines
888 B
Scala
36 lines
888 B
Scala
package BACK
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import chisel3._
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import chisel3.util._
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trait LocalRegisters { this: BackBoardSlvBase =>
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val digitalDir = RegInit(0.U(32.W))
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val digitalOut = RegInit(0.U(32.W))
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val digitalIn = WireDefault(0.U(32.W))
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registersRD := Mux1H(Seq(
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(upStreamReq.io.latDat.bits.register === 0.U) -> digitalDir,
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(upStreamReq.io.latDat.bits.register === 1.U) -> digitalIn,
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))
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when( upStreamReq.io.latDat.fire & upStreamReq.io.latDat.bits.address(5,1) === io.localHost & upStreamReq.io.latDat.bits.address.extract(0) === 1.U ){
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when(upStreamReq.io.latDat.bits.register === 0.U){
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digitalDir := upStreamReq.io.latDat.bits.data
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}
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when(upStreamReq.io.latDat.bits.register === 1.U){
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digitalOut := upStreamReq.io.latDat.bits.data
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}
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}
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val led = IO(Output(UInt(3.W)))
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val sw = IO( Input(UInt(1.W)))
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led := digitalOut(2,0)
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digitalIn := sw
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} |