1701 lines
50 KiB
Scala
1701 lines
50 KiB
Scala
package MAC
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import chisel3._
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import chisel3.util._
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class MacTileLinkIO extends Bundle{
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// WISHBONE common
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val WB_DAT_I = Input(UInt(32.W)) // WISHBONE data input
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val WB_DAT_O = Output(UInt(32.W)) // WISHBONE data output
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// WISHBONE slave
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val WB_ADR_I = Input(UInt(8.W)) // WISHBONE address input
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val WB_WE_I = Input(Bool()) // WISHBONE write enable input
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val BDCs = Input(UInt(4.W)) // Buffer descriptors are selected
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val WB_ACK_O = Output(Bool()) // WISHBONE acknowledge output
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// WISHBONE master
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val m_wb_adr_o = Output(UInt(30.W))
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val m_wb_sel_o = Output(UInt(4.W))
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val m_wb_we_o = Output(Bool())
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val m_wb_dat_o = Output(UInt(32.W))
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val m_wb_cyc_o = Output(Bool())
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val m_wb_stb_o = Output(Bool())
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val m_wb_dat_i = Input(UInt(32.W))
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val m_wb_ack_i = Input(Bool())
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val m_wb_err_i = Input(Bool())
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val m_wb_cti_o = Output(UInt(3.W)) // Cycle Type Identifier
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val m_wb_bte_o = Output(UInt(2.W)) // Burst Type Extension
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// Rx Status signals
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val InvalidSymbol = Input(Bool()) // Invalid symbol was received during reception in 100 Mbps mode
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val LatchedCrcError = Input(Bool()) // CRC error
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val RxLateCollision = Input(Bool()) // Late collision occured while receiving frame
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val ShortFrame = Input(Bool()) // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
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val DribbleNibble = Input(Bool()) // Extra nibble received
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val ReceivedPacketTooBig = Input(Bool()) // Received packet is bigger than r_MaxFL
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val RxLength = Input(UInt(16.W)) // Length of the incoming frame
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val LoadRxStatus = Input(Bool()) // Rx status was loaded
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val ReceivedPacketGood = Input(Bool()) // Received packet's length and CRC are good
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val AddressMiss = Input(Bool()) // When a packet is received AddressMiss status is written to the Rx BD
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val r_RxFlow = Input(Bool())
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val r_PassAll = Input(Bool())
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val ReceivedPauseFrm = Input(Bool())
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// Tx Status signals
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val RetryCntLatched = Input(UInt(4.W)) // Latched Retry Counter
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val RetryLimit = Input(Bool()) // Retry limit reached (Retry Max value +1 attempts were made)
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val LateCollLatched = Input(Bool()) // Late collision occured
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val DeferLatched = Input(Bool()) // Defer indication (Frame was defered before sucessfully sent)
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val RstDeferLatched = Output(Bool())
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val CarrierSenseLost = Input(Bool()) // Carrier Sense was lost during the frame transmission
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// Tx
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val MTxClk = Input(Bool()) // Transmit clock (from PHY)
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val TxUsedData = Input(Bool()) // Transmit packet used data
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val TxRetry = Input(Bool()) // Transmit packet retry
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val TxAbort = Input(Bool()) // Transmit packet abort
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val TxDone = Input(Bool()) // Transmission ended
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val TxStartFrm = Output(Bool()) // Transmit packet start frame
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val TxEndFrm = Output(Bool()) // Transmit packet end frame
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val TxData = Output(UInt(8.W)) // Transmit packet data byte
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val TxUnderRun = Output(Bool()) // Transmit packet under-run
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val PerPacketCrcEn = Output(Bool()) // Per packet crc enable
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val PerPacketPad = Output(Bool()) // Per packet pading
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// Rx
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val MRxClk = Input(Bool()) // Receive clock (from PHY)
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val RxData = Input(UInt(8.W)) // Received data byte (from PHY)
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val RxValid = Input(Bool())
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val RxStartFrm = Input(Bool())
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val RxEndFrm = Input(Bool())
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val RxAbort = Input(Bool()) // This signal is set when address doesn't match.
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val RxStatusWriteLatched_sync2 = Output(Bool())
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//Register
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val r_TxEn = Input(Bool()) // Transmit enable
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val r_RxEn = Input(Bool()) // Receive enable
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val r_TxBDNum = Input(UInt(8.W)) // Receive buffer descriptor number
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// Interrupts
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val TxB_IRQ = Output(Bool())
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val TxE_IRQ = Output(Bool())
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val RxB_IRQ = Output(Bool())
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val RxE_IRQ = Output(Bool())
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val Busy_IRQ = Output(Bool())
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}
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abstract class MacTileLinkBase extends Module{
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val io: MacTileLinkIO = IO(new MacTileLinkIO)
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val TxB_IRQ = RegInit(false.B); io.TxB_IRQ := TxB_IRQ
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val TxE_IRQ = RegInit(false.B); io.TxE_IRQ := TxE_IRQ
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val RxB_IRQ = RegInit(false.B); io.RxB_IRQ := RxB_IRQ
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val RxE_IRQ = RegInit(false.B); io.RxE_IRQ := RxE_IRQ
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val TxUnderRun_wb = RegInit(false.B)
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val TxBDRead = RegInit(true.B)
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val TxStatusWrite = Wire(Bool())
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val TxValidBytesLatched = RegInit(0.U(2.W))
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val TxLength = RegInit(0.U(16.W))
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val LatchedTxLength = RegInit(0.U(16.W))
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val TxStatus = RegInit(0.U(4.W)) //[14:11]
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val RxStatus = RegInit(0.U(2.W)) //[14:13]
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// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
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// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
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// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
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val TxRetrySync1 = RegNext(io.TxRetry, false.B)
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val TxAbortSync1 = RegNext(io.TxAbort, false.B)
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val TxDoneSync1 = RegNext(io.TxDone, false.B)
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val TxStartFrm_wb = RegInit(false.B)
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val TxRetry_wb = RegNext(TxRetrySync1, false.B)
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val TxAbort_wb = RegNext(TxAbortSync1, false.B)
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val TxDone_wb = RegNext(TxDoneSync1, false.B)
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// Generating delayed signals
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val TxDone_wb_q = RegNext(TxDone_wb, false.B)
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val TxAbort_wb_q = RegNext(TxAbort_wb, false.B)
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val TxRetry_wb_q = RegNext(TxRetry_wb, false.B)
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val TxRetryPacket = RegInit(false.B)
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val TxRetryPacket_NotCleared = RegInit(false.B)
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val TxDonePacket = RegInit(false.B)
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val TxDonePacket_NotCleared = RegInit(false.B)
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val TxAbortPacket = RegInit(false.B)
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val TxAbortPacket_NotCleared = RegInit(false.B)
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val RxBDReady = RegInit(false.B)
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val RxReady = RegInit(false.B)
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val TxBDReady = RegInit(false.B)
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val RxBDRead = RegInit(false.B)
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val BlockingTxStatusWrite = RegInit(false.B)
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val BlockingTxBDRead = RegInit(false.B)
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val RxBDAddress = RegInit(0.U(7.W)) //[7:1]
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val TxBDAddress = RegInit(0.U(7.W)) //[7:1]
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val ShiftEnded = RegInit(false.B)
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val RxOverrun = RegInit(false.B)
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val BDWrite = RegInit(0.U(4.W)) // BD Write Enable for access from WISHBONE side
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val BDRead = RegInit(false.B) // BD Read access from WISHBONE side
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val RxBDDataIn = Wire(UInt(32.W)) // Rx BD data in
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val TxBDDataIn = Wire(UInt(32.W)) // Tx BD data in
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val TxEndFrm_wb = RegInit(false.B)
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val TxRetryPulse = Wire(Bool())
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val TxDonePulse = Wire(Bool())
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val TxAbortPulse = Wire(Bool())
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val StartRxBDRead = Wire(Bool())
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val StartTxBDRead = Wire(Bool())
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val TxIRQEn = Wire(Bool())
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val WrapTxStatusBit = Wire(Bool())
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val RxIRQEn = Wire(Bool())
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val WrapRxStatusBit = Wire(Bool())
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val TxValidBytes = Wire(UInt(2.W))
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val TempTxBDAddress = Wire(UInt(7.W)) //[7:1]
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val TempRxBDAddress = Wire(UInt(7.W)) //[7:1]
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val RxStatusWrite = Wire(Bool())
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val RxBufferFull = Wire(Bool())
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val RxBufferAlmostEmpty = Wire(Bool())
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val RxBufferEmpty = Wire(Bool())
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val WB_ACK_O = Reg(Bool()); io.WB_ACK_O := WB_ACK_O
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val RxStatusIn = Wire(UInt(9.W))
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// Delayed stage signals
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val WbEn = RegInit(true.B)
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val WbEn_q = RegNext(WbEn, false.B)
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val RxEn = RegInit(false.B)
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val RxEn_q = RegNext(RxEn, false.B)
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val TxEn = RegInit(false.B)
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val TxEn_q = RegNext(TxEn, false.B)
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val r_TxEn_q = RegNext(io.r_TxEn, false.B)
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val r_RxEn_q = RegNext(io.r_RxEn, false.B)
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val ram_ce = true.B
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val ram_we = Wire(UInt(4.W))
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val ram_oe = Wire(Bool())
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val ram_addr = RegInit(0.U(8.W))
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val ram_di = RegInit(0.U(32.W))
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val ram_do = Wire(UInt(32.W))
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val StartTxPointerRead = Wire(Bool())
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val TxPointerRead = RegInit(false.B)
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val TxEn_needed = RegInit(false.B)
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val RxEn_needed = RegInit(false.B)
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val StartRxPointerRead = Wire(Bool())
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val RxPointerRead = RegInit(false.B)
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// RX shift ending signals
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val ShiftEnded_rck_txclk = Wire(Bool())
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val ShiftEndedSync1 = RegNext( ShiftEnded_rck_txclk, false.B)
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val ShiftEndedSync2 = RegNext( ShiftEndedSync1, false.B)
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val ShiftEndedSync3 = RegInit(false.B)
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val StartShiftWillEnd = Wire(Bool())
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val StartOccured = RegInit(false.B)
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val TxStartFrm_syncb1 = RegInit(false.B)
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val TxStartFrm_syncb2 = RegInit(false.B)
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val TxFifoClear = Wire(Bool())
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val TxBufferAlmostFull = Wire(Bool())
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val TxBufferFull = Wire(Bool())
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val TxBufferEmpty = Wire(Bool())
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val TxBufferAlmostEmpty = Wire(Bool())
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val SetReadTxDataFromMemory = Wire(Bool())
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val BlockReadTxDataFromMemory = RegInit(false.B)
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val tx_burst_en = RegInit(true.B)
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val rx_burst_en = RegInit(false.B)
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val tx_burst_cnt = RegInit(0.U(3.W))
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val ReadTxDataFromMemory_2 = Wire(Bool())
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val tx_burst = Wire(Bool())
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val m_wb_cti_o = RegInit(0.U(3.W)); io.m_wb_cti_o := m_wb_cti_o // Cycle Type Identifier
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val TxData_wb = Wire(UInt(32.W))
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val ReadTxDataFromFifo_wb = Wire(Bool())
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val txfifo_cnt = Wire(UInt(5.W))
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val rxfifo_cnt = Wire(UInt(5.W))
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val rx_burst_cnt = RegInit(0.U(3.W))
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val rx_burst = Wire(Bool())
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val enough_data_in_rxfifo_for_burst = Wire(Bool())
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val enough_data_in_rxfifo_for_burst_plus1 = Wire(Bool())
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val ReadTxDataFromMemory = RegInit(false.B)
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val WriteRxDataToMemory = Wire(Bool())
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val MasterWbTX = RegInit(false.B)
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val MasterWbRX = RegInit(false.B)
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val m_wb_adr_o = RegInit(0.U(30.W)); io.m_wb_adr_o := m_wb_adr_o
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val m_wb_cyc_o = RegInit(false.B); io.m_wb_cyc_o := m_wb_cyc_o
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val m_wb_sel_o = RegInit(0.U(4.W)); io.m_wb_sel_o := m_wb_sel_o
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val m_wb_we_o = RegInit(false.B); io.m_wb_we_o := m_wb_we_o
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val TxLengthEq0 = Wire(Bool())
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val TxLengthLt4 = Wire(Bool())
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val BlockingIncrementTxPointer = RegInit(false.B)
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val TxPointerMSB = RegInit(0.U(30.W)) //[31:2]
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val TxPointerLSB = RegInit(0.U(2.W))
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val TxPointerLSB_rst = RegInit(0.U(2.W))
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val RxPointerMSB = RegInit(0.U(30.W)) //[31:2]
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val RxPointerLSB_rst = RegInit(0.U(2.W))
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val ResetTxBDReady = Wire(Bool())
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val cyc_cleared = RegInit(false.B)
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val IncrTxPointer = RegInit(false.B)
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val RxByteSel = Wire(UInt(4.W))
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val MasterAccessFinished = Wire(Bool())
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val LatchValidBytes = RegInit(false.B)
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val LatchValidBytes_q = RegNext(LatchValidBytes, false.B)
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// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
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// Synchronizing TxStartFrm_wb to MTxClk
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val ReadTxDataFromFifo_tck_txclk = Wire(Bool())
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val ReadTxDataFromFifo_sync1 = RegNext(ReadTxDataFromFifo_tck_txclk, false.B)
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val ReadTxDataFromFifo_sync2 = RegNext(ReadTxDataFromFifo_sync1, false.B)
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val ReadTxDataFromFifo_sync3 = RegNext(ReadTxDataFromFifo_sync2, false.B)
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val RxAbortLatched_rxclk = Wire(Bool())
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val RxAbortSync1 = RegNext( RxAbortLatched_rxclk, false.B )
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val RxAbortSync2 = RegNext( RxAbortSync1, false.B )
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val RxAbortSync3 = RegNext( RxAbortSync2, false.B )
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val RxAbortSync4 = RegNext( RxAbortSync3, false.B )
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val SetWriteRxDataToFifo = Wire(Bool())
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val WriteRxDataToFifo_rxclk = Wire(Bool())
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val WriteRxDataToFifoSync1 = RegNext( WriteRxDataToFifo_rxclk, false.B)
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val WriteRxDataToFifoSync2 = RegNext( WriteRxDataToFifoSync1, false.B)
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val WriteRxDataToFifoSync3 = RegNext( WriteRxDataToFifoSync2, false.B)
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val WriteRxDataToFifo_wb = Wire(Bool())
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val LatchedRxStartFrm_rxclk = Wire(Bool())
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val SyncRxStartFrm = RegNext( LatchedRxStartFrm_rxclk, false.B)
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val SyncRxStartFrm_q = RegNext( SyncRxStartFrm, false.B)
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val SyncRxStartFrm_q2 = RegNext( SyncRxStartFrm_q, false.B)
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val RxFifoReset = Wire(Bool())
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val TxError = Wire(Bool())
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val RxError = Wire(Bool())
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val RxStatusWriteLatched = RegInit(false.B)
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val RxStatusWriteLatched_syncb1 = RegNext(io.RxStatusWriteLatched_sync2, false.B)
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val RxStatusWriteLatched_syncb2 = RegNext(RxStatusWriteLatched_syncb1, false.B)
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io.m_wb_bte_o := "b00".U // Linear burst
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io.m_wb_stb_o := m_wb_cyc_o
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when(true.B){
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WB_ACK_O := (BDWrite.orR & WbEn & WbEn_q) | (BDRead & WbEn & ~WbEn_q)
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}
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// Generic synchronous single-port RAM interface
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val bd_ram = Module(new MacSRAM)
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io.WB_DAT_O := ram_do
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bd_ram.io.ce := ram_ce
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bd_ram.io.we := ram_we.asBools
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bd_ram.io.oe := ram_oe
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bd_ram.io.addr := ram_addr
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bd_ram.io.di := ram_di
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ram_do := bd_ram.io.dato
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ram_we :=
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(BDWrite & Fill(4,(WbEn & WbEn_q)) ) |
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Fill(4, (TxStatusWrite | RxStatusWrite) )
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ram_oe :=
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(BDRead & WbEn & WbEn_q) |
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(TxEn & TxEn_q & (TxBDRead | TxPointerRead)) |
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(RxEn & RxEn_q & (RxBDRead | RxPointerRead))
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when(~TxBDReady & io.r_TxEn & WbEn & ~WbEn_q){
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TxEn_needed := true.B
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} .elsewhen(TxPointerRead & TxEn & TxEn_q){
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TxEn_needed := false.B
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}
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// Enabling access to the RAM for three devices.
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val RAMAccessEnable =
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Cat(WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed)
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// Switching between three stages depends on enable signals
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when( RAMAccessEnable === "b10010".U | RAMAccessEnable === "b10011".U ){ // synopsys parallel_case
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WbEn := false.B
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RxEn := true.B // wb access stage and r_RxEn is enabled
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TxEn := false.B
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ram_addr := Cat(RxBDAddress, RxPointerRead)
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ram_di := RxBDDataIn
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} .elsewhen( RAMAccessEnable === "b10001".U ){
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WbEn := false.B
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RxEn := false.B
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TxEn := true.B // wb access stage, r_RxEn is disabled but r_TxEn is enabled
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ram_addr := Cat(TxBDAddress, TxPointerRead)
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ram_di := TxBDDataIn;
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} .elsewhen( RAMAccessEnable === "b01000".U | RAMAccessEnable === "b01010".U ){
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WbEn := true.B // RxEn access stage and r_TxEn is disabled
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RxEn := false.B
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TxEn := false.B
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ram_addr := io.WB_ADR_I // [9:2];
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ram_di := io.WB_DAT_I;
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BDWrite := io.BDCs & Fill(4,io.WB_WE_I)
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BDRead := io.BDCs.orR & ~io.WB_WE_I
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} .elsewhen( RAMAccessEnable === "b01001".U | RAMAccessEnable === "b01011".U ){
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WbEn := false.B
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RxEn := false.B
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TxEn := true.B // RxEn access stage and r_TxEn is enabled
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ram_addr := Cat(TxBDAddress, TxPointerRead)
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ram_di := TxBDDataIn;
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} .elsewhen( RAMAccessEnable === "b00100".U | RAMAccessEnable === "b00101".U | RAMAccessEnable === "b00110".U | RAMAccessEnable === "b00111".U ){
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WbEn := true.B // TxEn access stage (we always go to wb access stage)
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RxEn := false.B
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TxEn := false.B
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ram_addr := io.WB_ADR_I //[9:2]
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ram_di := io.WB_DAT_I
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BDWrite := io.BDCs & Fill(4,io.WB_WE_I)
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BDRead := io.BDCs.orR & ~io.WB_WE_I
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} .elsewhen( RAMAccessEnable === "b10000".U ){
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WbEn := false.B // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
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} .elsewhen( RAMAccessEnable === "b00000".U ){
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WbEn := true.B // Idle state. We go to WbEn access stage.
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RxEn := false.B
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TxEn := false.B
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ram_addr := io.WB_ADR_I //[9:2]
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ram_di := io.WB_DAT_I
|
|
BDWrite := io.BDCs & Fill(4,io.WB_WE_I)
|
|
BDRead := io.BDCs.orR & ~io.WB_WE_I
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
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|
|
|
|
|
|
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|
|
|
|
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|
|
|
|
|
ResetTxBDReady := TxDonePulse | TxAbortPulse | TxRetryPulse
|
|
|
|
|
|
// Latching READY status of the Tx buffer descriptor
|
|
when(TxEn & TxEn_q & TxBDRead){ // TxBDReady is sampled only once at the beginning.
|
|
TxBDReady := ram_do.extract(15) & (ram_do(31,16) > 4.U)
|
|
} .elsewhen(ResetTxBDReady){ // Only packets larger then 4 bytes are transmitted.
|
|
TxBDReady := false.B
|
|
}
|
|
|
|
|
|
StartTxBDRead := (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady // Reading the Tx buffer descriptor
|
|
|
|
when(StartTxBDRead){
|
|
TxBDRead := true.B
|
|
} .elsewhen(TxBDReady){
|
|
TxBDRead := false.B
|
|
}
|
|
|
|
StartTxPointerRead := TxBDRead & TxBDReady // Reading Tx BD pointer
|
|
|
|
// Reading Tx BD Pointer
|
|
when(StartTxPointerRead){
|
|
TxPointerRead := true.B
|
|
} .elsewhen(TxEn_q){
|
|
TxPointerRead := false.B
|
|
}
|
|
|
|
|
|
|
|
// Writing status back to the Tx buffer descriptor
|
|
TxStatusWrite := (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite
|
|
|
|
|
|
// Status writing must occur only once. Meanwhile it is blocked.
|
|
when(~TxDone_wb & ~TxAbort_wb){
|
|
BlockingTxStatusWrite := false.B
|
|
} .elsewhen(TxStatusWrite){
|
|
BlockingTxStatusWrite := true.B
|
|
}
|
|
|
|
|
|
|
|
|
|
val BlockingTxStatusWrite_sync2_txclk = Wire(Bool())
|
|
val BlockingTxStatusWrite_sync3_txclk = Wire(Bool())
|
|
io.RstDeferLatched := BlockingTxStatusWrite_sync2_txclk & ~BlockingTxStatusWrite_sync3_txclk
|
|
|
|
// TxBDRead state is activated only once.
|
|
when(StartTxBDRead){
|
|
BlockingTxBDRead := true.B
|
|
} .elsewhen(~StartTxBDRead & ~TxBDReady){
|
|
BlockingTxBDRead := false.B
|
|
}
|
|
|
|
|
|
|
|
// Latching status from the tx buffer descriptor
|
|
// Data is avaliable one cycle after the access is started (at that time
|
|
// signal TxEn is not active)
|
|
when(TxEn & TxEn_q & TxBDRead){
|
|
TxStatus := ram_do(14,11)
|
|
}
|
|
|
|
|
|
|
|
|
|
//Latching length from the buffer descriptor;
|
|
when(TxEn & TxEn_q & TxBDRead){
|
|
TxLength := ram_do(31,16)
|
|
} .elsewhen(MasterWbTX & io.m_wb_ack_i){
|
|
when(TxLengthLt4){
|
|
TxLength := 0.U
|
|
} .elsewhen(TxPointerLSB_rst === 0.U){
|
|
TxLength := TxLength - 4.U // Length is subtracted at the data request
|
|
} .elsewhen(TxPointerLSB_rst === 1.U){
|
|
TxLength := TxLength - 3.U // Length is subtracted at the data request
|
|
} .elsewhen(TxPointerLSB_rst === 2.U){
|
|
TxLength := TxLength - 2.U // Length is subtracted at the data request
|
|
} .elsewhen(TxPointerLSB_rst === 3.U){
|
|
TxLength := TxLength - 1.U // Length is subtracted at the data request
|
|
}
|
|
}
|
|
|
|
|
|
//Latching length from the buffer descriptor;
|
|
when(TxEn & TxEn_q & TxBDRead){
|
|
LatchedTxLength := ram_do(31,16)
|
|
}
|
|
|
|
|
|
|
|
TxLengthEq0 := TxLength === 0.U
|
|
TxLengthLt4 := TxLength < 4.U
|
|
|
|
|
|
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are
|
|
// latched because TxPointerMSB is only used for word-aligned accesses.
|
|
when(TxEn & TxEn_q & TxPointerRead){
|
|
TxPointerMSB := ram_do(31,2)
|
|
} .elsewhen(IncrTxPointer & ~BlockingIncrementTxPointer){
|
|
TxPointerMSB := TxPointerMSB + 1.U // TxPointer is word-aligned
|
|
}
|
|
|
|
|
|
|
|
|
|
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed, valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This signals are used for proper selection of the star byte (TxData and TxByteCnt) are set by this two bits.
|
|
when(TxEn & TxEn_q & TxPointerRead){
|
|
TxPointerLSB := ram_do(1,0)
|
|
}
|
|
|
|
|
|
|
|
// Latching 2 MSB bits of the buffer descriptor. After the read access, TxLength needs to be decremented for the number of the valid bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are valid so this two bits are reset to zero.
|
|
when(TxEn & TxEn_q & TxPointerRead){
|
|
TxPointerLSB_rst := ram_do(1,0)
|
|
} .elsewhen(MasterWbTX & io.m_wb_ack_i){ // After first access pointer is word alligned
|
|
TxPointerLSB_rst := 0.U
|
|
}
|
|
|
|
|
|
|
|
when(MasterAccessFinished){
|
|
BlockingIncrementTxPointer := false.B
|
|
} .elsewhen(IncrTxPointer){
|
|
BlockingIncrementTxPointer := true.B
|
|
}
|
|
|
|
|
|
SetReadTxDataFromMemory := TxEn & TxEn_q & TxPointerRead;
|
|
|
|
when(TxLengthEq0 | TxAbortPulse | TxRetryPulse){
|
|
ReadTxDataFromMemory := false.B
|
|
} .elsewhen(SetReadTxDataFromMemory){
|
|
ReadTxDataFromMemory := true.B
|
|
}
|
|
|
|
|
|
ReadTxDataFromMemory_2 := ReadTxDataFromMemory & ~BlockReadTxDataFromMemory
|
|
|
|
tx_burst := ReadTxDataFromMemory_2 & tx_burst_en
|
|
|
|
|
|
|
|
when((TxBufferAlmostFull | TxLength <= 4.U) & MasterWbTX & (~cyc_cleared) & (~(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared))){
|
|
BlockReadTxDataFromMemory := true.B
|
|
} .elsewhen(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket){
|
|
BlockReadTxDataFromMemory := false.B
|
|
}
|
|
|
|
MasterAccessFinished := io.m_wb_ack_i | io.m_wb_err_i
|
|
|
|
|
|
|
|
// Enabling master wishbone access to the memory for two devices TX and RX.
|
|
|
|
val masterStage = Cat(MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst)
|
|
|
|
// Switching between two stages depends on enable signals
|
|
|
|
|
|
when(
|
|
masterStage === BitPat("b00100010") | // Idle and MRB needed
|
|
masterStage === BitPat("b101?101?") | // MRB continues
|
|
masterStage === BitPat("b10100110") | // Clear (previously MR) and MRB needed
|
|
masterStage === BitPat("b011?011?")
|
|
){ // Clear (previously MW) and MRB needed
|
|
MasterWbTX := true.B // tx burst
|
|
MasterWbRX := false.B
|
|
m_wb_cyc_o := true.B
|
|
m_wb_we_o := false.B
|
|
m_wb_sel_o := "hf".U
|
|
cyc_cleared := false.B
|
|
IncrTxPointer := true.B
|
|
tx_burst_cnt := tx_burst_cnt + 1.U
|
|
when(tx_burst_cnt === 0.U){
|
|
m_wb_adr_o := TxPointerMSB
|
|
} .otherwise{
|
|
m_wb_adr_o := m_wb_adr_o + 1.U
|
|
}
|
|
|
|
when(tx_burst_cnt === 3.U) {
|
|
tx_burst_en := false.B
|
|
m_wb_cti_o := "b111".U
|
|
} .otherwise{
|
|
m_wb_cti_o := "b010".U
|
|
}
|
|
} .elsewhen(
|
|
masterStage === BitPat("b00?100?1") | // Idle and MWB needed
|
|
masterStage === BitPat("b01?110?1") | // MWB continues
|
|
masterStage === BitPat("b01010101") | // Clear (previously MW) and MWB needed
|
|
masterStage === BitPat("b10?101?1") // Clear (previously MR) and MWB needed
|
|
){
|
|
MasterWbTX := false.B // rx burst
|
|
MasterWbRX := true.B
|
|
m_wb_cyc_o := true.B
|
|
m_wb_we_o := true.B
|
|
m_wb_sel_o := RxByteSel
|
|
IncrTxPointer := false.B
|
|
cyc_cleared := false.B
|
|
rx_burst_cnt := rx_burst_cnt + 1.U
|
|
|
|
when(rx_burst_cnt === 0.U ){
|
|
m_wb_adr_o := RxPointerMSB
|
|
} .otherwise{
|
|
m_wb_adr_o := m_wb_adr_o + 1.U
|
|
}
|
|
|
|
when(rx_burst_cnt === 3.U ){
|
|
rx_burst_en := false.B
|
|
m_wb_cti_o := "b111".U
|
|
} .otherwise{
|
|
m_wb_cti_o := "b010".U
|
|
}
|
|
}.elsewhen( masterStage === BitPat("b00?100?0") ){ // idle and MW is needed (data write to rx buffer)
|
|
MasterWbTX := false.B
|
|
MasterWbRX := true.B
|
|
m_wb_adr_o := RxPointerMSB
|
|
m_wb_cyc_o := true.B
|
|
m_wb_we_o := true.B
|
|
m_wb_sel_o := RxByteSel
|
|
IncrTxPointer := false.B
|
|
}.elsewhen( masterStage === BitPat("b00100000") ){ // idle and MR is needed (data read from tx buffer)
|
|
MasterWbTX := true.B
|
|
MasterWbRX := false.B
|
|
m_wb_adr_o := TxPointerMSB;
|
|
m_wb_cyc_o := true.B
|
|
m_wb_we_o := false.B
|
|
m_wb_sel_o := "hf".U
|
|
IncrTxPointer := true.B
|
|
}.elsewhen(
|
|
masterStage === BitPat("b10100100") | // MR and MR is needed (data read from tx buffer)
|
|
masterStage === BitPat("b011?010?") // MW and MR is needed (data read from tx buffer)
|
|
){
|
|
MasterWbTX := true.B
|
|
MasterWbRX := false.B
|
|
m_wb_adr_o := TxPointerMSB;
|
|
m_wb_cyc_o := true.B
|
|
m_wb_we_o := false.B
|
|
m_wb_sel_o := "hf".U
|
|
cyc_cleared := false.B
|
|
IncrTxPointer := true.B
|
|
}.elsewhen(
|
|
masterStage === BitPat("b01010100") | // MW and MW needed (data write to rx buffer)
|
|
masterStage === BitPat("b10?101?0") // MR and MW is needed (data write to rx buffer)
|
|
){
|
|
MasterWbTX := false.B
|
|
MasterWbRX := true.B
|
|
m_wb_adr_o := RxPointerMSB;
|
|
m_wb_cyc_o := true.B
|
|
m_wb_we_o := true.B
|
|
m_wb_sel_o := RxByteSel;
|
|
cyc_cleared := false.B
|
|
IncrTxPointer := false.B
|
|
}.elsewhen(
|
|
masterStage === BitPat("b01011000") | // MW and MW needed (cycle is cleared between previous and next access)
|
|
masterStage === BitPat("b011?10?0") | // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
|
|
masterStage === BitPat("b10101000") | // MR and MR needed (cycle is cleared between previous and next access)
|
|
masterStage === BitPat("b10?1100?") // MR and MR or MW or MWB (cycle is cleared between previous and next access)
|
|
){
|
|
m_wb_cyc_o := false.B// whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
|
|
cyc_cleared := true.B
|
|
IncrTxPointer := false.B
|
|
tx_burst_cnt := 0.U
|
|
tx_burst_en := (txfifo_cnt < 12.U) & (TxLength > 20.U)
|
|
rx_burst_cnt := 0.U
|
|
rx_burst_en := Mux(MasterWbRX, enough_data_in_rxfifo_for_burst_plus1, enough_data_in_rxfifo_for_burst) // Counter is not decremented, yet, so plus1 is used.
|
|
m_wb_cti_o := 0.U
|
|
}.elsewhen(
|
|
masterStage === BitPat("b??001000") | // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
|
masterStage === BitPat("b??000100") // Between cyc_cleared request was cleared
|
|
){
|
|
MasterWbTX := false.B
|
|
MasterWbRX := false.B
|
|
m_wb_cyc_o := false.B
|
|
cyc_cleared := false.B
|
|
IncrTxPointer := false.B
|
|
rx_burst_cnt := 0.U
|
|
// Counter is not decremented, yet, so plus1 is used.
|
|
rx_burst_en := Mux(MasterWbRX, enough_data_in_rxfifo_for_burst_plus1, enough_data_in_rxfifo_for_burst)
|
|
m_wb_cti_o := 0.U
|
|
}.elsewhen( masterStage === BitPat("b00000000") ){ // whatever and no master read or write is needed (ack or err comes finishing previous access)
|
|
tx_burst_cnt := 0.U
|
|
tx_burst_en := (txfifo_cnt < 12.U) & (TxLength > 20.U)
|
|
} .otherwise{
|
|
|
|
}
|
|
|
|
|
|
|
|
TxFifoClear := (TxAbortPacket | TxRetryPacket)
|
|
|
|
val tx_fifo = Module( new MacFifo(dw = 32, dp = 16) )
|
|
tx_fifo.io.data_in := io.m_wb_dat_i
|
|
tx_fifo.io.write := MasterWbTX & io.m_wb_ack_i
|
|
tx_fifo.io.read := ReadTxDataFromFifo_wb & ~TxBufferEmpty
|
|
tx_fifo.io.clear := TxFifoClear
|
|
TxData_wb := tx_fifo.io.data_out
|
|
TxBufferFull := tx_fifo.io.full
|
|
TxBufferAlmostFull := tx_fifo.io.almost_full
|
|
TxBufferAlmostEmpty := tx_fifo.io.almost_empty
|
|
TxBufferEmpty := tx_fifo.io.empty
|
|
txfifo_cnt := tx_fifo.io.cnt
|
|
|
|
|
|
|
|
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
|
|
when(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0)){
|
|
TxStartFrm_wb := true.B
|
|
} .elsewhen(TxStartFrm_syncb2){
|
|
TxStartFrm_wb := false.B
|
|
}
|
|
|
|
|
|
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
|
|
when(TxStartFrm_wb){
|
|
StartOccured := true.B
|
|
} .elsewhen(ResetTxBDReady){
|
|
StartOccured := false.B
|
|
}
|
|
|
|
|
|
val TxStartFrm_sync2_txclk = Wire(Bool())
|
|
when(true.B){
|
|
TxStartFrm_syncb1 := TxStartFrm_sync2_txclk
|
|
TxStartFrm_syncb2 := TxStartFrm_syncb1
|
|
}
|
|
|
|
|
|
|
|
// TxEndFrm_wb: indicator of the end of frame
|
|
when(TxLengthEq0 & TxBufferAlmostEmpty & io.TxUsedData){
|
|
TxEndFrm_wb := true.B
|
|
} .elsewhen(TxRetryPulse | TxDonePulse | TxAbortPulse){
|
|
TxEndFrm_wb := false.B
|
|
}
|
|
|
|
|
|
// Marks which bytes are valid within the word.
|
|
TxValidBytes := Mux(TxLengthLt4, TxLength(1,0), 0.U)
|
|
|
|
|
|
|
|
when(TxLengthLt4 & TxBDReady){
|
|
LatchValidBytes := true.B
|
|
}.otherwise{
|
|
LatchValidBytes := false.B
|
|
}
|
|
|
|
|
|
// Latching valid bytes
|
|
when(LatchValidBytes & ~LatchValidBytes_q){
|
|
TxValidBytesLatched := TxValidBytes
|
|
} .elsewhen(TxRetryPulse | TxDonePulse | TxAbortPulse){
|
|
TxValidBytesLatched := 0.U
|
|
}
|
|
|
|
|
|
// dontTouch(TxStatus)
|
|
TxIRQEn := TxStatus.extract(3) //[14:11]
|
|
WrapTxStatusBit := TxStatus.extract(2)
|
|
io.PerPacketPad := TxStatus.extract(1)
|
|
io.PerPacketCrcEn := TxStatus.extract(0)
|
|
|
|
RxIRQEn := RxStatus.extract(1) //[14:13]
|
|
WrapRxStatusBit := RxStatus.extract(0)
|
|
|
|
|
|
// Temporary Tx and Rx buffer descriptor address
|
|
TempTxBDAddress := Fill(7, TxStatusWrite & ~WrapTxStatusBit) & (TxBDAddress + 1.U) // Tx BD increment or wrap (last BD)
|
|
|
|
TempRxBDAddress :=
|
|
( Fill(7, WrapRxStatusBit) & io.r_TxBDNum(6,0) ) | // Using first Rx BD
|
|
( Fill(7,~WrapRxStatusBit) & (RxBDAddress + 1.U)) // Using next Rx BD
|
|
// (increment address)
|
|
|
|
// Latching Tx buffer descriptor address
|
|
when(io.r_TxEn & (~r_TxEn_q)){
|
|
TxBDAddress := 0.U
|
|
} .elsewhen(TxStatusWrite){
|
|
TxBDAddress := TempTxBDAddress
|
|
}
|
|
|
|
// Latching Rx buffer descriptor address
|
|
when(io.r_RxEn & (~r_RxEn_q)){
|
|
RxBDAddress := io.r_TxBDNum(6,0)
|
|
} .elsewhen(RxStatusWrite){
|
|
RxBDAddress := TempRxBDAddress;
|
|
}
|
|
|
|
|
|
val TxStatusInLatched = Cat(io.TxUnderRun, io.RetryCntLatched, io.RetryLimit, io.LateCollLatched, io.DeferLatched, io.CarrierSenseLost)
|
|
val LatchedRxLength_rxclk = Wire(UInt(16.W))
|
|
val RxStatusInLatched_rxclk = Wire(UInt(9.W))
|
|
RxBDDataIn := Cat(LatchedRxLength_rxclk, 0.U(1.W), RxStatus, 0.U(4.W), RxStatusInLatched_rxclk)
|
|
TxBDDataIn := Cat(LatchedTxLength, 0.U(1.W), TxStatus, 0.U(2.W), TxStatusInLatched)
|
|
|
|
|
|
// Signals used for various purposes
|
|
TxRetryPulse := TxRetry_wb & ~TxRetry_wb_q
|
|
TxDonePulse := TxDone_wb & ~TxDone_wb_q
|
|
TxAbortPulse := TxAbort_wb & ~TxAbort_wb_q
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
val TxAbortPacketBlocked = RegInit(false.B)
|
|
|
|
when(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
|
|
(~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
|
|
(~TxAbortPacketBlocked)){
|
|
TxAbortPacket := true.B
|
|
} .otherwise{
|
|
TxAbortPacket := false.B
|
|
}
|
|
|
|
|
|
when(TxEn & TxEn_q & TxAbortPacket_NotCleared){
|
|
TxAbortPacket_NotCleared := false.B
|
|
} .elsewhen(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
|
|
(~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
|
|
(~TxAbortPacketBlocked)){
|
|
TxAbortPacket_NotCleared := true.B
|
|
}
|
|
|
|
when(~TxAbort_wb & TxAbort_wb_q){
|
|
TxAbortPacketBlocked := false.B
|
|
} .elsewhen(TxAbortPacket){
|
|
TxAbortPacketBlocked := true.B
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
val TxRetryPacketBlocked = RegInit(false.B)
|
|
|
|
when(
|
|
TxRetry_wb & ~tx_burst_en & MasterWbTX & MasterAccessFinished & ~TxRetryPacketBlocked |
|
|
TxRetry_wb & ~MasterWbTX & ~TxRetryPacketBlocked){
|
|
TxRetryPacket := true.B
|
|
} .otherwise{
|
|
TxRetryPacket := false.B
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
when(StartTxBDRead){
|
|
TxRetryPacket_NotCleared := false.B
|
|
} .elsewhen(
|
|
TxRetry_wb & ~tx_burst_en & MasterWbTX & MasterAccessFinished & ~TxRetryPacketBlocked |
|
|
TxRetry_wb & ~MasterWbTX & ~TxRetryPacketBlocked){
|
|
TxRetryPacket_NotCleared := true.B
|
|
}
|
|
|
|
|
|
when(~TxRetry_wb & TxRetry_wb_q){
|
|
TxRetryPacketBlocked := false.B
|
|
} .elsewhen(TxRetryPacket){
|
|
TxRetryPacketBlocked := true.B
|
|
}
|
|
|
|
|
|
|
|
val TxDonePacketBlocked = RegInit(false.B)
|
|
|
|
when(
|
|
TxDone_wb & ~tx_burst_en & MasterWbTX & MasterAccessFinished & ~TxDonePacketBlocked |
|
|
TxDone_wb & ~MasterWbTX & ~TxDonePacketBlocked){
|
|
TxDonePacket := true.B
|
|
}.otherwise{
|
|
TxDonePacket := false.B
|
|
}
|
|
|
|
when(TxEn & TxEn_q & TxDonePacket_NotCleared){
|
|
TxDonePacket_NotCleared := false.B
|
|
} .elsewhen(
|
|
TxDone_wb & ~tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
|
|
TxDone_wb & ~MasterWbTX & (~TxDonePacketBlocked)){
|
|
TxDonePacket_NotCleared := true.B
|
|
}
|
|
|
|
|
|
when(~TxDone_wb & TxDone_wb_q){
|
|
TxDonePacketBlocked := false.B
|
|
} .elsewhen(TxDonePacket){
|
|
TxDonePacketBlocked := true.B
|
|
}
|
|
|
|
|
|
|
|
// Tx under run
|
|
when(TxAbortPulse){
|
|
TxUnderRun_wb := false.B
|
|
} .elsewhen(TxBufferEmpty & ReadTxDataFromFifo_wb){
|
|
TxUnderRun_wb := true.B
|
|
}
|
|
|
|
|
|
ReadTxDataFromFifo_wb := ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3
|
|
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
|
|
|
|
|
|
StartRxBDRead :=
|
|
RxStatusWrite |
|
|
RxAbortSync3 & ~RxAbortSync4 |
|
|
io.r_RxEn & ~r_RxEn_q
|
|
|
|
// Reading the Rx buffer descriptor
|
|
when(StartRxBDRead & ~RxReady){
|
|
RxBDRead := true.B
|
|
} .elsewhen(RxBDReady){
|
|
RxBDRead := false.B
|
|
}
|
|
|
|
|
|
|
|
// Reading of the next receive buffer descriptor starts after reception status
|
|
// is written to the previous one.
|
|
|
|
// Latching READY status of the Rx buffer descriptor
|
|
when(RxPointerRead){
|
|
RxBDReady := false.B
|
|
} .elsewhen(RxEn & RxEn_q & RxBDRead){
|
|
RxBDReady := ram_do.extract(15)// RxBDReady is sampled only once at the beginning
|
|
}
|
|
|
|
|
|
// Latching Rx buffer descriptor status
|
|
// Data is avaliable one cycle after the access is started (at that time
|
|
// signal RxEn is not active)
|
|
when(RxEn & RxEn_q & RxBDRead){
|
|
RxStatus := ram_do(14,13)
|
|
}
|
|
|
|
|
|
|
|
// RxReady generation
|
|
when(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~io.r_RxEn & r_RxEn_q){
|
|
RxReady := false.B
|
|
} .elsewhen(RxEn & RxEn_q & RxPointerRead){
|
|
RxReady := true.B
|
|
}
|
|
|
|
// Reading Rx BD pointer
|
|
StartRxPointerRead := RxBDRead & RxBDReady
|
|
|
|
// Reading Tx BD Pointer
|
|
when(StartRxPointerRead){
|
|
RxPointerRead := true.B
|
|
} .elsewhen(RxEn & RxEn_q){
|
|
RxPointerRead := false.B
|
|
}
|
|
|
|
|
|
|
|
//Latching Rx buffer pointer from buffer descriptor;
|
|
when(RxEn & RxEn_q & RxPointerRead){
|
|
RxPointerMSB := ram_do(31,2)
|
|
} .elsewhen(MasterWbRX & io.m_wb_ack_i){
|
|
RxPointerMSB := RxPointerMSB + 1.U // Word access (always word access. m_wb_sel_o are used for selecting bytes)
|
|
}
|
|
|
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
|
|
when(MasterWbRX & io.m_wb_ack_i){// After first write all RxByteSel are active
|
|
RxPointerLSB_rst := 0.U
|
|
} .elsewhen(RxEn & RxEn_q & RxPointerRead){
|
|
RxPointerLSB_rst := ram_do(1,0)
|
|
}
|
|
|
|
RxByteSel := Mux1H(Seq(
|
|
(RxPointerLSB_rst === 0.U) -> "hf".U,
|
|
(RxPointerLSB_rst === 1.U) -> "h7".U,
|
|
(RxPointerLSB_rst === 2.U) -> "h3".U,
|
|
(RxPointerLSB_rst === 3.U) -> "h1".U,
|
|
))
|
|
|
|
|
|
when(~RxReady & io.r_RxEn & WbEn & ~WbEn_q){
|
|
RxEn_needed := true.B
|
|
} .elsewhen(RxPointerRead & RxEn & RxEn_q){
|
|
RxEn_needed := false.B
|
|
}
|
|
|
|
|
|
|
|
// Reception status is written back to the buffer descriptor after the end of frame is detected.
|
|
RxStatusWrite := ShiftEnded & RxEn & RxEn_q
|
|
|
|
|
|
|
|
|
|
val LastByteIn_rxclk = Wire(Bool())
|
|
val RxByteCnt_rxclk = Wire(UInt(2.W))
|
|
val RxEnableWindow_rxclk = Wire(Bool())
|
|
StartShiftWillEnd := LastByteIn_rxclk | io.RxValid & io.RxEndFrm & RxByteCnt_rxclk.andR & RxEnableWindow_rxclk
|
|
|
|
// Indicating start of the reception process
|
|
val ShiftWillEnd_rxclk = Wire(Bool())
|
|
SetWriteRxDataToFifo :=
|
|
(io.RxValid & RxReady & ~io.RxStartFrm & RxEnableWindow_rxclk & (RxByteCnt_rxclk.andR)) |
|
|
(io.RxValid & RxReady & io.RxStartFrm & (RxPointerLSB_rst.andR)) |
|
|
(ShiftWillEnd_rxclk & LastByteIn_rxclk & (RxByteCnt_rxclk.andR))
|
|
|
|
|
|
|
|
WriteRxDataToFifo_wb := WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3
|
|
|
|
|
|
|
|
RxFifoReset := SyncRxStartFrm_q & ~SyncRxStartFrm_q2
|
|
|
|
val rx_fifo = Module(new MacFifo(dw = 32, dp = 16))
|
|
val RxDataLatched2_rxclk = Wire(UInt(32.W))
|
|
rx_fifo.io.data_in := RxDataLatched2_rxclk
|
|
rx_fifo.io.write := WriteRxDataToFifo_wb & ~RxBufferFull
|
|
rx_fifo.io.read := MasterWbRX & io.m_wb_ack_i
|
|
rx_fifo.io.clear := RxFifoReset
|
|
|
|
io.m_wb_dat_o := rx_fifo.io.data_out
|
|
RxBufferFull := rx_fifo.io.full
|
|
RxBufferAlmostEmpty := rx_fifo.io.almost_empty
|
|
RxBufferEmpty := rx_fifo.io.empty
|
|
rxfifo_cnt := rx_fifo.io.cnt
|
|
|
|
|
|
|
|
enough_data_in_rxfifo_for_burst := rxfifo_cnt >= 4.U
|
|
enough_data_in_rxfifo_for_burst_plus1 := rxfifo_cnt > 4.U
|
|
|
|
WriteRxDataToMemory := ~RxBufferEmpty
|
|
rx_burst := rx_burst_en & WriteRxDataToMemory
|
|
|
|
|
|
|
|
|
|
|
|
when(ShiftEndedSync1 & ~ShiftEndedSync2){
|
|
ShiftEndedSync3 := true.B
|
|
} .elsewhen(ShiftEnded){
|
|
ShiftEndedSync3 := false.B
|
|
}
|
|
|
|
|
|
// Generation of the end-of-frame signal
|
|
when(ShiftEndedSync3 & MasterWbRX & io.m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded){
|
|
ShiftEnded := true.B
|
|
} .elsewhen(RxStatusWrite){
|
|
ShiftEnded := false.B
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
RxStatusIn := Cat(io.ReceivedPauseFrm, io.AddressMiss, RxOverrun, io.InvalidSymbol, io.DribbleNibble, io.ReceivedPacketTooBig, io.ShortFrame, io.LatchedCrcError, io.RxLateCollision)
|
|
|
|
|
|
// Rx overrun
|
|
when(RxStatusWrite){
|
|
RxOverrun := false.B
|
|
} .elsewhen(RxBufferFull & WriteRxDataToFifo_wb){
|
|
RxOverrun := true.B
|
|
}
|
|
|
|
|
|
|
|
|
|
TxError := io.TxUnderRun | io.RetryLimit | io.LateCollLatched | io.CarrierSenseLost
|
|
|
|
|
|
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames are aborted when signal r_RecSmall is set to 0 in MODER register.
|
|
// AddressMiss is identifying that a frame was received because of the promiscous mode and is not an error
|
|
RxError := (RxStatusInLatched_rxclk(6,3).orR) | (RxStatusInLatched_rxclk(1,0).orR)
|
|
|
|
|
|
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
|
|
when(RxStatusWriteLatched_syncb2){
|
|
RxStatusWriteLatched := false.B
|
|
} .elsewhen(RxStatusWrite){
|
|
RxStatusWriteLatched := true.B
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Tx Done Interrupt
|
|
when(TxStatusWrite & TxIRQEn){
|
|
TxB_IRQ := ~TxError
|
|
} .otherwise{
|
|
TxB_IRQ := false.B
|
|
}
|
|
|
|
// Tx Error Interrupt
|
|
when(TxStatusWrite & TxIRQEn){
|
|
TxE_IRQ := TxError
|
|
} .otherwise{
|
|
TxE_IRQ := false.B
|
|
}
|
|
|
|
// Rx Done Interrupt
|
|
when(RxStatusWrite & RxIRQEn & io.ReceivedPacketGood & (~io.ReceivedPauseFrm | io.ReceivedPauseFrm & io.r_PassAll & (~io.r_RxFlow))){
|
|
RxB_IRQ := (~RxError)
|
|
} .otherwise{
|
|
RxB_IRQ := false.B
|
|
}
|
|
|
|
// Rx Error Interrupt
|
|
when(RxStatusWrite & RxIRQEn & (~io.ReceivedPauseFrm | io.ReceivedPauseFrm & io.r_PassAll & (~io.r_RxFlow))){
|
|
RxE_IRQ := RxError
|
|
} .otherwise{
|
|
RxE_IRQ := false.B
|
|
}
|
|
|
|
|
|
|
|
|
|
// Busy Interrupt
|
|
val Busy_IRQ_rck_rxclk = Wire(Bool())
|
|
val Busy_IRQ_sync1 = RegNext(Busy_IRQ_rck_rxclk)
|
|
val Busy_IRQ_sync2 = RegNext(Busy_IRQ_sync1)
|
|
val Busy_IRQ_sync3 = RegNext(Busy_IRQ_sync2)
|
|
val Busy_IRQ_syncb1 = Reg(Bool())
|
|
val Busy_IRQ_syncb2 = Reg(Bool())
|
|
|
|
|
|
|
|
|
|
|
|
io.Busy_IRQ := Busy_IRQ_sync2 & ~Busy_IRQ_sync3
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
trait MacTileLinkTXClk{ this: MacTileLinkBase =>
|
|
withClockAndReset( io.MTxClk.asClock, reset ) {
|
|
|
|
val Flop = Reg(Bool())
|
|
val BlockingTxStatusWrite_sync1 = Reg(Bool())
|
|
val BlockingTxStatusWrite_sync2 = Reg(Bool()); BlockingTxStatusWrite_sync2_txclk := BlockingTxStatusWrite_sync2
|
|
val BlockingTxStatusWrite_sync3 = Reg(Bool()); BlockingTxStatusWrite_sync3_txclk := BlockingTxStatusWrite_sync3
|
|
val TxStartFrm_sync1 = Reg(Bool())
|
|
val TxStartFrm_sync2 = Reg(Bool()); TxStartFrm_sync2_txclk := TxStartFrm_sync2
|
|
val TxStartFrm = Reg(Bool()); io.TxStartFrm := TxStartFrm
|
|
val TxEndFrm = Reg(Bool()); io.TxEndFrm := TxEndFrm
|
|
val TxData = Reg(UInt(8.W)); io.TxData := TxData
|
|
val TxUnderRun = Reg(Bool()); io.TxUnderRun := TxUnderRun
|
|
val TxDataLatched = Reg(UInt(32.W))
|
|
val TxByteCnt = Reg(UInt(2.W))
|
|
val LastWord = Reg(Bool())
|
|
val ReadTxDataFromFifo_tck = Reg(Bool()); ReadTxDataFromFifo_tck_txclk := ReadTxDataFromFifo_tck
|
|
val TxAbort_q = Reg(Bool())
|
|
val TxRetry_q = Reg(Bool())
|
|
val TxUsedData_q = Reg(Bool())
|
|
val ReadTxDataFromFifo_syncb1 = Reg(Bool())
|
|
val ReadTxDataFromFifo_syncb2 = Reg(Bool())
|
|
val ReadTxDataFromFifo_syncb3 = Reg(Bool())
|
|
|
|
// Changes for tx occur every second clock. Flop is used for this manner.
|
|
when(reset.asBool){
|
|
Flop := false.B
|
|
} .elsewhen( io.TxDone | io.TxAbort | TxRetry_q){
|
|
Flop := false.B
|
|
} .elsewhen ( io.TxUsedData ){
|
|
Flop := ~Flop
|
|
}
|
|
|
|
// Synchronizing BlockingTxStatusWrite to MTxClk
|
|
when(reset.asBool){
|
|
BlockingTxStatusWrite_sync1 := false.B
|
|
BlockingTxStatusWrite_sync2 := false.B
|
|
BlockingTxStatusWrite_sync3 := false.B
|
|
} .otherwise{
|
|
BlockingTxStatusWrite_sync1 := BlockingTxStatusWrite;
|
|
BlockingTxStatusWrite_sync2 := BlockingTxStatusWrite_sync1;
|
|
BlockingTxStatusWrite_sync3 := BlockingTxStatusWrite_sync2;
|
|
}
|
|
|
|
// Synchronizing TxStartFrm_wb to MTxClk
|
|
when(reset.asBool){
|
|
TxStartFrm_sync1 := false.B
|
|
TxStartFrm_sync2 := false.B
|
|
} .otherwise{
|
|
TxStartFrm_sync1 := TxStartFrm_wb
|
|
TxStartFrm_sync2 := TxStartFrm_sync1;
|
|
}
|
|
|
|
|
|
when(reset.asBool){
|
|
TxStartFrm := false.B
|
|
} .elsewhen(TxStartFrm_sync2){
|
|
TxStartFrm := true.B
|
|
} .elsewhen(TxUsedData_q | ~TxStartFrm_sync2 & (io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q))){
|
|
TxStartFrm := false.B
|
|
}
|
|
|
|
// Generating delayed signals
|
|
when(reset.asBool){
|
|
TxAbort_q := false.B
|
|
TxRetry_q := false.B
|
|
TxUsedData_q := false.B
|
|
} .otherwise{
|
|
TxAbort_q := io.TxAbort
|
|
TxRetry_q := io.TxRetry
|
|
TxUsedData_q := io.TxUsedData
|
|
}
|
|
|
|
// Indication of the last word
|
|
when(reset.asBool){
|
|
LastWord := false.B
|
|
} .elsewhen( (TxEndFrm | io.TxAbort | io.TxRetry) & Flop ){
|
|
LastWord := false.B
|
|
} .elsewhen( io.TxUsedData & Flop & TxByteCnt === 3.U ){
|
|
LastWord := TxEndFrm_wb
|
|
}
|
|
|
|
// Tx end frame generation
|
|
when(reset.asBool){
|
|
TxEndFrm := false.B
|
|
} .elsewhen(Flop & TxEndFrm | io.TxAbort | TxRetry_q){
|
|
TxEndFrm := false.B
|
|
} .elsewhen(Flop & LastWord){
|
|
TxEndFrm :=
|
|
Mux1H(Seq(
|
|
(TxValidBytesLatched === 1.U) -> (TxByteCnt === 0.U),
|
|
(TxValidBytesLatched === 2.U) -> (TxByteCnt === 1.U),
|
|
(TxValidBytesLatched === 3.U) -> (TxByteCnt === 2.U),
|
|
(TxValidBytesLatched === 0.U) -> (TxByteCnt === 3.U),
|
|
))
|
|
}
|
|
|
|
|
|
|
|
// Tx data selection (latching)
|
|
when(reset.asBool){
|
|
TxData := 0.U
|
|
} .elsewhen( TxStartFrm_sync2 & ~TxStartFrm ){
|
|
TxData := Mux1H(Seq(
|
|
( TxPointerLSB === 0.U ) -> TxData_wb(31,24),// Big Endian Byte Ordering
|
|
( TxPointerLSB === 1.U ) -> TxData_wb(23,16),// Big Endian Byte Ordering
|
|
( TxPointerLSB === 2.U ) -> TxData_wb(15, 8),// Big Endian Byte Ordering
|
|
( TxPointerLSB === 3.U ) -> TxData_wb( 7, 0),// Big Endian Byte Ordering
|
|
))
|
|
} .elsewhen( TxStartFrm & io.TxUsedData & TxPointerLSB === 3.U ){
|
|
TxData := TxData_wb(31,24) // Big Endian Byte Ordering
|
|
} .elsewhen(io.TxUsedData & Flop){
|
|
TxData := Mux1H(Seq(
|
|
(TxByteCnt === 0.U) -> TxDataLatched(31,24),// Big Endian Byte Ordering
|
|
(TxByteCnt === 1.U) -> TxDataLatched(23,16),
|
|
(TxByteCnt === 2.U) -> TxDataLatched(15, 8),
|
|
(TxByteCnt === 3.U) -> TxDataLatched( 7, 0),
|
|
))
|
|
}
|
|
|
|
|
|
|
|
// Latching tx data
|
|
when(reset.asBool){
|
|
TxDataLatched := 0.U
|
|
} .elsewhen(
|
|
TxStartFrm_sync2 & ~TxStartFrm |
|
|
io.TxUsedData & Flop & TxByteCnt === 3.U |
|
|
TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U){
|
|
TxDataLatched := TxData_wb
|
|
}
|
|
|
|
|
|
val TxUnderRun_sync1 = Reg(Bool())
|
|
|
|
// Tx under run
|
|
when(reset.asBool){
|
|
TxUnderRun_sync1 := false.B
|
|
} .elsewhen(TxUnderRun_wb){
|
|
TxUnderRun_sync1 := true.B
|
|
} .elsewhen(BlockingTxStatusWrite_sync2){
|
|
TxUnderRun_sync1 := false.B
|
|
}
|
|
|
|
|
|
// Tx under run
|
|
when(reset.asBool){
|
|
TxUnderRun := false.B
|
|
} .elsewhen(BlockingTxStatusWrite_sync2){
|
|
TxUnderRun := false.B
|
|
} .elsewhen(TxUnderRun_sync1){
|
|
TxUnderRun := true.B
|
|
}
|
|
|
|
|
|
|
|
// Tx Byte counter
|
|
when(reset.asBool){
|
|
TxByteCnt := 0.U
|
|
} .elsewhen(TxAbort_q | TxRetry_q){
|
|
TxByteCnt := 0.U
|
|
} .elsewhen(TxStartFrm & ~io.TxUsedData){
|
|
TxByteCnt := Mux1H(Seq(
|
|
( TxPointerLSB === 0.U ) -> 1.U,
|
|
( TxPointerLSB === 1.U ) -> 2.U,
|
|
( TxPointerLSB === 2.U ) -> 3.U,
|
|
( TxPointerLSB === 3.U ) -> 0.U,
|
|
))
|
|
} .elsewhen(io.TxUsedData & Flop){
|
|
TxByteCnt := TxByteCnt + 1.U
|
|
}
|
|
|
|
when(reset.asBool){
|
|
ReadTxDataFromFifo_tck := false.B
|
|
} .elsewhen(TxStartFrm_sync2 & ~TxStartFrm | io.TxUsedData & Flop & TxByteCnt === 3.U &
|
|
~LastWord | TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){
|
|
ReadTxDataFromFifo_tck := true.B
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} .elsewhen(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3){
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ReadTxDataFromFifo_tck := false.B
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}
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when(reset.asBool){
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ReadTxDataFromFifo_syncb1 := false.B
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ReadTxDataFromFifo_syncb2 := false.B
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ReadTxDataFromFifo_syncb3 := false.B
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}.otherwise{
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ReadTxDataFromFifo_syncb1 := ReadTxDataFromFifo_sync2;
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ReadTxDataFromFifo_syncb2 := ReadTxDataFromFifo_syncb1;
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ReadTxDataFromFifo_syncb3 := ReadTxDataFromFifo_syncb2;
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}
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}
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}
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trait MacTileLinkRXClk{ this: MacTileLinkBase =>
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withClockAndReset( io.MRxClk.asClock, reset ){
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val RxDataLatched2 = Reg(UInt(32.W)); RxDataLatched2_rxclk := RxDataLatched2
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val RxDataLatched1 = Reg(UInt(24.W)) // Big Endian Byte Ordering[31:8]
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val RxValidBytes = Reg(UInt(2.W))
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val RxByteCnt = Reg(UInt(2.W)); RxByteCnt_rxclk := RxByteCnt
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val LastByteIn = Reg(Bool()); LastByteIn_rxclk := LastByteIn
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val ShiftWillEnd = Reg(Bool()); ShiftWillEnd_rxclk := ShiftWillEnd
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val WriteRxDataToFifo = Reg(Bool()); WriteRxDataToFifo_rxclk := WriteRxDataToFifo
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val LatchedRxLength = Reg(UInt(16.W)); LatchedRxLength_rxclk := LatchedRxLength
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val RxAbortLatched = Reg(Bool()); RxAbortLatched_rxclk := RxAbortLatched
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val RxStatusInLatched = Reg(UInt(9.W)); RxStatusInLatched_rxclk := RxStatusInLatched
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val ShiftEnded_rck = Reg(Bool()); ShiftEnded_rck_txclk := ShiftEnded_rck
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val ShiftEndedSync_c1 = Reg(Bool())
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val ShiftEndedSync_c2 = Reg(Bool())
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val RxAbortSyncb1 = Reg(Bool())
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val RxAbortSyncb2 = Reg(Bool())
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val RxEnableWindow = Reg(Bool()); RxEnableWindow_rxclk := RxEnableWindow
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val LatchedRxStartFrm = Reg(Bool()); LatchedRxStartFrm_rxclk := LatchedRxStartFrm
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val RxStatusWriteLatched_sync1 = Reg(Bool())
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val RxStatusWriteLatched_sync2 = Reg(Bool()); io.RxStatusWriteLatched_sync2 := RxStatusWriteLatched_sync2
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// Indicating that last byte is being reveived
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when(reset.asBool){
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LastByteIn := false.B
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} .elsewhen(ShiftWillEnd & RxByteCnt.andR | io.RxAbort){
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LastByteIn := false.B
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} .elsewhen(io.RxValid & RxReady & io.RxEndFrm & ~(RxByteCnt.andR) & RxEnableWindow){
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LastByteIn := true.B
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}
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// Indicating that data reception will end
|
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when(reset.asBool){
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ShiftWillEnd := false.B
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} .elsewhen(ShiftEnded_rck | io.RxAbort){
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ShiftWillEnd := false.B
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} .elsewhen(StartShiftWillEnd){
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ShiftWillEnd := true.B
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}
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// Receive byte counter
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when(reset.asBool){
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RxByteCnt := 0.U
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} .elsewhen(ShiftEnded_rck | io.RxAbort){
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RxByteCnt := 0.U
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} .elsewhen(io.RxValid & io.RxStartFrm & RxReady){
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RxByteCnt := Mux1H(Seq(
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( RxPointerLSB_rst === 0.U ) -> 1.U,
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( RxPointerLSB_rst === 1.U ) -> 2.U,
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( RxPointerLSB_rst === 2.U ) -> 3.U,
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( RxPointerLSB_rst === 3.U ) -> 0.U,
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))
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} .elsewhen(io.RxValid & RxEnableWindow & RxReady | LastByteIn){
|
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RxByteCnt := RxByteCnt + 1.U
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}
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// Indicates how many bytes are valid within the last word
|
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when(reset.asBool){
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RxValidBytes := 1.U
|
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} .elsewhen(io.RxValid & io.RxStartFrm){
|
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RxValidBytes := Mux1H(Seq(
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( RxPointerLSB_rst === 0.U ) -> 1.U,
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( RxPointerLSB_rst === 1.U ) -> 2.U,
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( RxPointerLSB_rst === 2.U ) -> 3.U,
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( RxPointerLSB_rst === 3.U ) -> 0.U,
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))
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} .elsewhen(io.RxValid & ~LastByteIn & ~io.RxStartFrm & RxEnableWindow){
|
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RxValidBytes := RxValidBytes + 1.U
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}
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when(reset.asBool){
|
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RxDataLatched1 := 0.U
|
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} .elsewhen(io.RxValid & RxReady & ~LastByteIn){
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when(io.RxStartFrm){
|
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RxDataLatched1 := Mux1H(Seq(
|
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( RxPointerLSB_rst === 0.U ) -> Cat( io.RxData, RxDataLatched1(15,0)),// Big Endian Byte Ordering
|
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( RxPointerLSB_rst === 1.U ) -> Cat(RxDataLatched1(23,16), io.RxData, RxDataLatched1( 7,0)),
|
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( RxPointerLSB_rst === 2.U ) -> Cat(RxDataLatched1(23, 8), io.RxData),
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( RxPointerLSB_rst === 3.U ) -> RxDataLatched1,
|
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))
|
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} .elsewhen(RxEnableWindow){
|
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RxDataLatched1 := Mux1H(Seq(
|
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( RxByteCnt === 0.U ) -> Cat( io.RxData, RxDataLatched1(15,0)),// Big Endian Byte Ordering
|
|
( RxByteCnt === 1.U ) -> Cat(RxDataLatched1(23,16), io.RxData, RxDataLatched1( 7,0)),
|
|
( RxByteCnt === 2.U ) -> Cat(RxDataLatched1(23, 8), io.RxData),
|
|
( RxByteCnt === 3.U ) -> RxDataLatched1,
|
|
))
|
|
}
|
|
}
|
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|
|
// Assembling data that will be written to the rx_fifo
|
|
when(reset.asBool){
|
|
RxDataLatched2 := 0.U
|
|
} .elsewhen(SetWriteRxDataToFifo & ~ShiftWillEnd){
|
|
RxDataLatched2 := Cat(RxDataLatched1, io.RxData)// Big Endian Byte Ordering
|
|
} .elsewhen(SetWriteRxDataToFifo & ShiftWillEnd){
|
|
RxDataLatched2 := Mux1H(Seq(
|
|
( RxValidBytes === 0.U ) -> Cat(RxDataLatched1, io.RxData),
|
|
( RxValidBytes === 1.U ) -> Cat(RxDataLatched1(23,16), 0.U(24.W)),
|
|
( RxValidBytes === 2.U ) -> Cat(RxDataLatched1(23, 8), 0.U(16.W)),
|
|
( RxValidBytes === 3.U ) -> Cat(RxDataLatched1, 0.U(8.W)),
|
|
))
|
|
}
|
|
|
|
when(reset.asBool){
|
|
WriteRxDataToFifo := false.B
|
|
} .elsewhen(SetWriteRxDataToFifo & ~io.RxAbort){
|
|
WriteRxDataToFifo := true.B
|
|
} .elsewhen(WriteRxDataToFifoSync2 | io.RxAbort){
|
|
WriteRxDataToFifo := false.B
|
|
}
|
|
|
|
|
|
when(reset.asBool){
|
|
LatchedRxStartFrm := false.B
|
|
} .elsewhen(io.RxStartFrm & ~SyncRxStartFrm_q){
|
|
LatchedRxStartFrm := true.B
|
|
} .elsewhen(SyncRxStartFrm_q){
|
|
LatchedRxStartFrm := false.B
|
|
}
|
|
|
|
|
|
// Generation of the end-of-frame signal
|
|
when(reset.asBool){
|
|
ShiftEnded_rck := false.B
|
|
} .elsewhen(~io.RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd){
|
|
ShiftEnded_rck := true.B
|
|
} .elsewhen(io.RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2){
|
|
ShiftEnded_rck := false.B
|
|
}
|
|
|
|
|
|
|
|
when(reset.asBool){
|
|
ShiftEndedSync_c1 := false.B
|
|
ShiftEndedSync_c2 := false.B
|
|
} .otherwise{
|
|
ShiftEndedSync_c1 := ShiftEndedSync2
|
|
ShiftEndedSync_c2 := ShiftEndedSync_c1
|
|
}
|
|
|
|
|
|
// Generation of the end-of-frame signal
|
|
when(reset.asBool){
|
|
RxEnableWindow := false.B
|
|
} .elsewhen(io.RxStartFrm){
|
|
RxEnableWindow := true.B
|
|
} .elsewhen(io.RxEndFrm | io.RxAbort){
|
|
RxEnableWindow := false.B
|
|
}
|
|
|
|
|
|
when(reset.asBool){
|
|
RxAbortSyncb1 := false.B
|
|
RxAbortSyncb2 := false.B
|
|
} .otherwise{
|
|
RxAbortSyncb1 := RxAbortSync2
|
|
RxAbortSyncb2 := RxAbortSyncb1
|
|
}
|
|
|
|
|
|
when(reset.asBool){
|
|
RxAbortLatched := false.B
|
|
} .elsewhen(RxAbortSyncb2){
|
|
RxAbortLatched := false.B
|
|
} .elsewhen(io.RxAbort){
|
|
RxAbortLatched := true.B
|
|
}
|
|
|
|
|
|
when(reset.asBool){
|
|
LatchedRxLength := 0.U
|
|
} .elsewhen(io.LoadRxStatus){
|
|
LatchedRxLength := io.RxLength
|
|
}
|
|
|
|
|
|
when(reset.asBool){
|
|
RxStatusInLatched := 0.U
|
|
} .elsewhen(io.LoadRxStatus){
|
|
RxStatusInLatched := RxStatusIn
|
|
}
|
|
|
|
|
|
when(reset.asBool){
|
|
RxStatusWriteLatched_sync1 := false.B
|
|
RxStatusWriteLatched_sync2 := false.B
|
|
} .otherwise{
|
|
RxStatusWriteLatched_sync1 := RxStatusWriteLatched;
|
|
RxStatusWriteLatched_sync2 := RxStatusWriteLatched_sync1;
|
|
}
|
|
|
|
|
|
|
|
val Busy_IRQ_rck = Reg(Bool()); Busy_IRQ_rck_rxclk := Busy_IRQ_rck
|
|
|
|
when(reset.asBool){
|
|
Busy_IRQ_rck := false.B
|
|
} .elsewhen(io.RxValid & io.RxStartFrm & ~RxReady){
|
|
Busy_IRQ_rck := true.B
|
|
} .elsewhen(Busy_IRQ_syncb2){
|
|
Busy_IRQ_rck := false.B
|
|
}
|
|
|
|
when(true.B){
|
|
Busy_IRQ_syncb1 := Busy_IRQ_sync2
|
|
Busy_IRQ_syncb2 := Busy_IRQ_syncb1
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
class MacTileLink extends MacTileLinkBase with MacTileLinkTXClk with MacTileLinkRXClk
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// trait MacTileLinkSlave{ this: MacTileLinkBase =>
|
|
|
|
// val a = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
|
|
// val d = new DecoupledIO(new TLBundleD(edge.bundle))
|
|
|
|
// val tlSlvDValid = RegInit(false.B); io.d.valid := tlSlvDValid
|
|
|
|
|
|
// }
|
|
|