138 lines
3.6 KiB
Plaintext
138 lines
3.6 KiB
Plaintext
.PHONY:com sim clean
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OUTPUT = shin_test
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CPU_COUNT := $(shell nproc)
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VCS = vcs -sverilog +v2k -timescale=1ns/1ps \
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-full64 \
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-o ${OUTPUT} \
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-l compile.log \
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-debug_access+none \
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+define+VCS_COMPILE \
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-fastpartcomp=j${CPU_COUNT} \
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SIM = ./${OUTPUT} -l run.log
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testShin_vcs:
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python3 ./shinTest/gen_pkt.py
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mkdir -p generated/log
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rm -rf generated/log/*
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@echo "Available CPUs: ${CPU_COUNT}"
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${VCS} -f ./shinTest_vcs.f
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${SIM}
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python3 ./shinTest/check_testcase.py
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testShin8b10b_vcs:
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python3 ./shinTest/gen_pkt.py -8b10b
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mkdir -p generated/log
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rm -rf generated/log/*
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@echo "Available CPUs: ${CPU_COUNT}"
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${VCS} -f ./shinTest_vcs.f
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${SIM}
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python3 ./shinTest/check_testcase.py
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testShinClk_vcs:
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python3 ./shinTest/gen_pkt_clk.py --dev1 0 90 --dev2 0 -90
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mkdir -p generated/log
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rm -rf generated/log/*
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${VCS} -f ./shinTestClk_vcs.f
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${SIM}
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python3 ./shinTest/check_testcase.py
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mv spi_trans_data.txt generated/spi_trans_data1.txt
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mv generated/wave.vcd generated/wave1.vcd
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\
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python3 ./shinTest/gen_pkt_clk.py --dev1 45 180 --dev3 70 -180 -8b10b
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mkdir -p generated/log
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rm -rf generated/log/*
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${VCS} -f ./shinTestClk_vcs.f
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${SIM}
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python3 ./shinTest/check_testcase.py
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mv spi_trans_data.txt generated/spi_trans_data2.txt
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mv generated/wave.vcd generated/wave2.vcd
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\
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python3 ./shinTest/gen_pkt_clk.py --dev1 45 185 --dev3 25 -185
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mkdir -p generated/log
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rm -rf generated/log/*
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${VCS} -f ./shinTestClk_vcs.f
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${SIM}
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python3 ./shinTest/check_testcase.py
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mv spi_trans_data.txt generated/spi_trans_data3.txt
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mv generated/wave.vcd generated/wave3.vcd
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\
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python3 ./shinTest/gen_pkt_clk.py --dev1 60 186 --dev3 15 -186
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mkdir -p generated/log
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rm -rf generated/log/*
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${VCS} -f ./shinTestClk_vcs.f
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${SIM}
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python3 ./shinTest/check_testcase.py
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mv spi_trans_data.txt generated/spi_trans_data4.txt
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mv generated/wave.vcd generated/wave4.vcd
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\
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python3 ./shinTest/gen_pkt_clk.py --dev1 80 187 --dev2 30 -187
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mkdir -p generated/log
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rm -rf generated/log/*
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${VCS} -f ./shinTestClk_vcs.f
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${SIM}
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python3 ./shinTest/check_testcase.py
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mv spi_trans_data.txt generated/spi_trans_data5.txt
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mv generated/wave.vcd generated/wave5.vcd
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\
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python3 ./shinTest/gen_pkt_clk.py --dev1 70 188 --dev3 223 -188 -8b10b
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mkdir -p generated/log
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rm -rf generated/log/*
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${VCS} -f ./shinTestClk_vcs.f
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${SIM}
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python3 ./shinTest/check_testcase.py
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mv spi_trans_data.txt generated/spi_trans_data6.txt
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mv generated/wave.vcd generated/wave6.vcd
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testShinMany_vcs:
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python3 ./shinTest/gen_pkt_many_dev.py
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mkdir -p generated/log
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rm -rf generated/log/*
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@echo "Available CPUs: ${CPU_COUNT}"
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${VCS} -f ./shinTest_vcs.f
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${SIM}
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python3 ./shinTest/check_testcase.py
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sim:
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${SIM}
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testShin:
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./shinTest/gen_pkt.py
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mkdir -p generated/log
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rm -rf generated/log/*
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iverilog -Wall \
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-o ./generated/shinTest.iverilog \
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-y ./generated/shin \
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-I ./generated/shin \
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-D RANDOMIZE_REG_INIT \
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./shinTest/ShinTopSpiTb.v
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vvp -N ./generated/shinTest.iverilog -lxt2 -fst || true
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./shinTest/check_testcase.py
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testShinClk:
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./shinTest/gen_pkt_clk.py --dev1 0 200
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mkdir -p generated/log
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rm -rf generated/log/*
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iverilog -Wall \
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-o ./generated/shinTest_clk.iverilog \
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-y ./generated/shin \
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-I ./generated/shin \
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-D RANDOMIZE_REG_INIT \
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./shinTest/ShinTopSpiTb_clk.v
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vvp -N ./generated/shinTest_clk.iverilog -lxt2 -fst|| true
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./shinTest/check_testcase.py
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fstShin:
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gtkwave ./generated/wave.fst 1>/dev/null 2>&1 &
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fstShinClk:
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gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &
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clean:
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rm -rf ./generated/log/* ./generated/shin/*.vh ./generated/shinTest.* ./generated/wave*.* ./generated/spi_trans*.*
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