513 lines
16 KiB
Scala
513 lines
16 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class TopBase_IO_Bundle extends Bundle{
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val dDatIn = Input(Bool())
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val dDatOut = Output(Bool())
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val uDatIn = Input(Bool())
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val uDatOut = Output(Bool())
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val iqspi = new QSPIInterfaceIO
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val ospi = new SSPIInterfaceIO
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val oqspi = new QSPIInterfaceIO
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val iSync = Output(Vec(4, Bool()))
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val isSoftReset = Output(Bool())
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val interrupt = Output(Bool())
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val latchPin = Input(Vec(2, Bool()))
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val hwSerial = Input(UInt(48.W))
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val uniCode = Input(UInt(64.W))
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val pllCtrl = Output(UInt(32.W))
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val xtal = Output(UInt(12.W))
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val anamuxSel = Output(UInt(5.W))
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val ldo2p5 = Output(UInt(8.W))
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val ldo1p1 = Output(UInt(8.W))
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val refTop = Output(UInt(3.W))
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val bias = Output(UInt(2.W))
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val spiSel = Output(UInt(2.W))
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val isPllCfg = Output(Bool())
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}
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class MstSlvSwitchIO extends TopBase_IO_Bundle{
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val downCDROut = Flipped(new CDROutIO)
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val upCDROut = Flipped(new CDROutIO)
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val downCDRIn = Flipped(new CDRInIO)
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val upCDRIn = Flipped(new CDRInIO)
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}
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abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
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val io: MstSlvSwitchIO = IO(new MstSlvSwitchIO)
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val slaveParser = Module(new SlaveParser )
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val masterParser = Module(new MasterParser)
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val interface = Module(new Interface)
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interface.io.latchPin := io.latchPin
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interface.io.uniCode := io.uniCode
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interface.io.hwSerial := io.hwSerial
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interface.io.intTransEnd(0) := io.downCDRIn.axis.fire & io.downCDRIn.axis.bits.tlast
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interface.io.intTransEnd(1) := io.downCDROut.axis.fire & io.downCDROut.axis.bits.tlast
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interface.io.intTransEnd(2) := io.upCDRIn.axis.fire & io.upCDRIn.axis.bits.tlast
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interface.io.intTransEnd(3) := io.upCDROut.axis.fire & io.upCDROut.axis.bits.tlast
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io.isSoftReset := interface.io.isSoftReset
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io.interrupt := interface.io.interrupt
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io.ospi <> interface.io.ospi
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io.iqspi <> interface.io.iqspi
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io.oqspi <> interface.io.oqspi
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io.iSync := interface.io.sync
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io.pllCtrl := interface.io.cReg.pllCtrl
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io.xtal := interface.io.cReg.xtal
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io.anamuxSel := interface.io.cReg.anamuxSel
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io.ldo2p5 := interface.io.cReg.ldo2p5
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io.ldo1p1 := interface.io.cReg.ldo1p1
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io.refTop := interface.io.cReg.refTop
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io.bias := interface.io.cReg.bias
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io.spiSel := interface.io.cReg.spiSel
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io.isPllCfg := interface.io.isPllCfg
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val sram = Seq(
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for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
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for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
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for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
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for( _ <- 0 until 4 ) yield { Module(new ShareSRAM2k) },
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for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
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for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
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for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
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for( _ <- 0 until 2 ) yield { Module(new ShareSRAM2k) },
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)
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val smUnit = Seq(
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Module( new SMUnit(depth = 4) ),
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Module( new SMUnit(depth = 4) ),
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Module( new SMUnit(depth = 4) ),
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Module( new SMUnit(depth = 4) ),
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Module( new SMUnit(depth = 2) ),
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Module( new SMUnit(depth = 2) ),
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Module( new SMUnit(depth = 2) ),
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Module( new SMUnit(depth = 2) ),
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)
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val lvdsSMEnq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMEnq := lvdsSMEnq
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val lvdsSMDeq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMDeq := lvdsSMDeq
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smUnit(0).io.enq := lvdsSMEnq(0)
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smUnit(2).io.enq := lvdsSMEnq(1)
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smUnit(4).io.enq := lvdsSMEnq(2)
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smUnit(6).io.enq := lvdsSMEnq(3)
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smUnit(1).io.deq := lvdsSMDeq(0)
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smUnit(3).io.deq := lvdsSMDeq(1)
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smUnit(5).io.deq := lvdsSMDeq(2)
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smUnit(7).io.deq := lvdsSMDeq(3)
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smUnit(0).io.sram_r <> interface.io.sram_r(0)
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smUnit(2).io.sram_r <> interface.io.sram_r(1)
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smUnit(4).io.sram_r <> interface.io.sram_r(2)
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smUnit(6).io.sram_r <> interface.io.sram_r(3)
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smUnit(1).io.sram_w := interface.io.sram_w(0)
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smUnit(3).io.sram_w := interface.io.sram_w(1)
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smUnit(5).io.sram_w := interface.io.sram_w(2)
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smUnit(7).io.sram_w := interface.io.sram_w(3)
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smUnit(0).io.deq := interface.io.dSMdeq(0)
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smUnit(2).io.deq := interface.io.dSMdeq(1)
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smUnit(4).io.deq := interface.io.dSMdeq(2)
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smUnit(6).io.deq := interface.io.dSMdeq(3)
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smUnit(1).io.enq := interface.io.uSMenq(0)
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smUnit(3).io.enq := interface.io.uSMenq(1)
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smUnit(5).io.enq := interface.io.uSMenq(2)
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smUnit(7).io.enq := interface.io.uSMenq(3)
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for( i <- 0 until 8 ){
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interface.io.smUsedDepth(i) := smUnit(i).io.cnt
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smUnit(i).io.flush := interface.io.isSMReset(i)
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}
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for( i <- 0 until 4 ){
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for( j <- 0 until 4 ){
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sram(i)(j).io.clockr := clock.asBool
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sram(i)(j).io.clockw := clock.asBool
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smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
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sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
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sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
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sram(i)(j).io.enw := smUnit(i).io.sram(j).wr.enw
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sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
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sram(i)(j).io.enr := smUnit(i).io.sram(j).rd.enr
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}
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}
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for( i <- 4 until 8 ){
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for( j <- 0 until 2 ){
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sram(i)(j).io.clockr := clock.asBool
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sram(i)(j).io.clockw := clock.asBool
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smUnit(i).io.sram(j).rd.datar := sram(i)(j).io.datar
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sram(i)(j).io.dataw := smUnit(i).io.sram(j).wr.dataw
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sram(i)(j).io.addrw := smUnit(i).io.sram(j).wr.addrw
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sram(i)(j).io.enw := smUnit(i).io.sram(j).wr.enw
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sram(i)(j).io.addrr := smUnit(i).io.sram(j).rd.addrr
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sram(i)(j).io.enr := smUnit(i).io.sram(j).rd.enr
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}
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}
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//default
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{
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smUnit(0).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
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smUnit(2).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
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smUnit(4).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
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smUnit(6).io.sram_w := 0.U.asTypeOf(new SRAM2kWRIO)
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smUnit(1).io.sram_r.enr := false.B
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smUnit(3).io.sram_r.enr := false.B
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smUnit(5).io.sram_r.enr := false.B
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smUnit(7).io.sram_r.enr := false.B
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smUnit(1).io.sram_r.addrr := 0.U
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smUnit(3).io.sram_r.addrr := 0.U
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smUnit(5).io.sram_r.addrr := 0.U
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smUnit(7).io.sram_r.addrr := 0.U
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slaveParser.io.sram_r(0).datar := 0.U
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slaveParser.io.sram_r(1).datar := 0.U
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slaveParser.io.sram_r(2).datar := 0.U
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slaveParser.io.sram_r(3).datar := 0.U
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masterParser.io.sram_r.datar := 0.U
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io.downCDRIn.axis.ready := false.B
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slaveParser.io.downIn.valid := false.B
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slaveParser.io.downIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
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slaveParser.io.downOut.ready := false.B
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masterParser.io.downOut.ready := false.B
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io.downCDROut.axis.valid := false.B
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io.downCDROut.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
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io.upCDRIn.axis.ready := false.B
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slaveParser.io.upIn.valid := false.B
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slaveParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
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masterParser.io.upIn.valid := false.B
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masterParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
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slaveParser.io.upOut.ready := false.B
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io.upCDROut.axis.valid := false.B
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io.upCDROut.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
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interface.io.mstDeltaTime := 0.U
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interface.io.slvDeltaTime := 0.U
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interface.io.deltaFinal := 0.U
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interface.io.intMstTrig(0) := false.B
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interface.io.intMstTrig(1) := false.B
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interface.io.intSlvTrig(0) := false.B
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interface.io.intSlvTrig(1) := false.B
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interface.io.intSlvTrig(2) := false.B
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interface.io.intSlvTrig(3) := false.B
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interface.io.intSlvTrig(4) := false.B
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interface.io.intSlvTrig(5) := false.B
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interface.io.intSlvTrig(6) := false.B
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interface.io.intSlvTrig(7) := false.B
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interface.io.intHWTrig(0) := false.B
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interface.io.intHWTrig(1) := false.B
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interface.io.downRecStat := 0.U.asTypeOf(new Stat_IO_Bundle)
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interface.io.upRecStat := 0.U.asTypeOf(new Stat_IO_Bundle)
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}
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}
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trait MstSlvSwitchMaster{ this: MstSlvSwitchBase =>
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when( interface.io.cReg.modeSel === true.B ){
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masterParser.io.downOut <> io.downCDROut.axis
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masterParser.io.upIn <> io.upCDRIn.axis
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}
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when( interface.io.cReg.modeSel === true.B ){
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when( interface.io.txReq.bits.rxSM === 0.U ){
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smUnit(0).io.sram_w := masterParser.io.sram_w
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lvdsSMEnq(0) := masterParser.io.rxEnq
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} .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){
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smUnit(2).io.sram_w := masterParser.io.sram_w
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lvdsSMEnq(1) := masterParser.io.rxEnq
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} .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){
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smUnit(4).io.sram_w := masterParser.io.sram_w
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lvdsSMEnq(2) := masterParser.io.rxEnq
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} .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){
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smUnit(6).io.sram_w := masterParser.io.sram_w
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lvdsSMEnq(3) := masterParser.io.rxEnq
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}
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when( interface.io.txReq.bits.txSM === 0.U ){
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smUnit(1).io.sram_r <> masterParser.io.sram_r
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lvdsSMDeq(0) := masterParser.io.txDeq
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} .elsewhen( interface.io.txReq.bits.txSM === 1.U ){
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smUnit(3).io.sram_r <> masterParser.io.sram_r
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lvdsSMDeq(1) := masterParser.io.txDeq
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} .elsewhen( interface.io.txReq.bits.txSM === 2.U ){
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smUnit(5).io.sram_r <> masterParser.io.sram_r
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lvdsSMDeq(2) := masterParser.io.txDeq
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} .elsewhen( interface.io.txReq.bits.txSM === 3.U ){
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smUnit(7).io.sram_r <> masterParser.io.sram_r
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lvdsSMDeq(3) := masterParser.io.txDeq
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}
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interface.io.mstDeltaTime := masterParser.io.deltaTimeStamp
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interface.io.intMstTrig(0) := masterParser.io.txDeq
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interface.io.intMstTrig(1) := masterParser.io.rxEnq
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interface.io.downRecStat := 0.U.asTypeOf(new Stat_IO_Bundle)
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interface.io.upRecStat := masterParser.io.upRecStat
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}
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masterParser.io.req := interface.io.txReq.valid
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// masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength
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// io.rsp := masterParser.io.rsp
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masterParser.io.cReg := interface.io.cReg
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masterParser.io.mReg := interface.io.mReg
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}
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trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>
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when( interface.io.cReg.modeSel === false.B ){
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slaveParser.io.downIn <> io.downCDRIn.axis
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io.downCDROut.axis <> slaveParser.io.downOut
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slaveParser.io.upIn <> io.upCDRIn.axis
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io.upCDROut.axis <> slaveParser.io.upOut
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}
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slaveParser.io.cReg := interface.io.cReg
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slaveParser.io.sReg := interface.io.sReg
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when( interface.io.cReg.modeSel === false.B ){
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smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
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smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
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smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
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smUnit(6).io.sram_w := slaveParser.io.sram_w(3)
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smUnit(1).io.sram_r <> slaveParser.io.sram_r(0)
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smUnit(3).io.sram_r <> slaveParser.io.sram_r(1)
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smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
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smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)
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lvdsSMEnq(0) := slaveParser.io.dSMenq(0)
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lvdsSMEnq(1) := slaveParser.io.dSMenq(1)
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lvdsSMEnq(2) := slaveParser.io.dSMenq(2)
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lvdsSMEnq(3) := slaveParser.io.dSMenq(3)
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lvdsSMDeq(0) := slaveParser.io.uSMdeq(0)
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lvdsSMDeq(1) := slaveParser.io.uSMdeq(1)
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lvdsSMDeq(2) := slaveParser.io.uSMdeq(2)
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lvdsSMDeq(3) := slaveParser.io.uSMdeq(3)
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interface.io.mstDeltaTime := slaveParser.io.mstDeltaTimeStamp
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interface.io.slvDeltaTime := slaveParser.io.slvDeltaTime
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interface.io.deltaFinal := slaveParser.io.deltaFinal
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interface.io.intSlvTrig(0) := slaveParser.io.dSMenq(0)
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interface.io.intSlvTrig(1) := slaveParser.io.uSMdeq(0)
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interface.io.intSlvTrig(2) := slaveParser.io.dSMenq(1)
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interface.io.intSlvTrig(3) := slaveParser.io.uSMdeq(1)
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interface.io.intSlvTrig(4) := slaveParser.io.dSMenq(2)
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interface.io.intSlvTrig(5) := slaveParser.io.uSMdeq(2)
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interface.io.intSlvTrig(6) := slaveParser.io.dSMenq(3)
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interface.io.intSlvTrig(7) := slaveParser.io.uSMdeq(3)
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interface.io.intHWTrig(0) := slaveParser.io.intHWTrig(0)
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interface.io.intHWTrig(1) := slaveParser.io.intHWTrig(1)
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interface.io.downRecStat := slaveParser.io.downRecStat
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interface.io.upRecStat := slaveParser.io.upRecStat
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}
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slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0)
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slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1)
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io.downCDRIn.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
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io.upCDRIn.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
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io.downCDROut.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
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io.upCDROut.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
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interface.io.lvds <> slaveParser.io.lvds
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interface.io.localDevIndex := slaveParser.io.localDevIndex
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//从站链路寄存器
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// interface.io.isDevOnLeft := slaveParser.io.isDevOnLeft
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// interface.io.isDevOnLeftModify := slaveParser.io.isDevOnLeftModify
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// interface.io.indexOfLeftDev := slaveParser.io.indexOfLeftDev
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interface.io.isDevOnRight := slaveParser.io.isDevOnRight
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interface.io.isDevOnRightModify := slaveParser.io.isDevOnRightModify
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interface.io.indexOfRightDev := slaveParser.io.indexOfRightDev
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}
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trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
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//看门狗1~16，SM监控
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val isWdtSMEnable = for( _ <- 0 until 16 ) yield { RegInit(false.B) }
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val wdtSMCnt = for( _ <- 0 until 16 ) yield { Reg(UInt(32.W)) }
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for( i <- 0 until 8 ){
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when( smUnit(i).io.enq ){
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isWdtSMEnable(2*i) := false.B
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} .elsewhen( ~isWdtSMEnable(2*i) & smUnit(i).io.sram_w.enw & interface.io.cReg.wdtEnable.extract(i+1) ){
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isWdtSMEnable(2*i) := true.B
|
||
}
|
||
|
||
when( smUnit(i).io.deq ){
|
||
isWdtSMEnable(2*i + 1) := false.B
|
||
} .elsewhen( ~isWdtSMEnable(2*i + 1) & smUnit(i).io.sram_r.enr & interface.io.cReg.wdtEnable.extract(i+1) ){
|
||
isWdtSMEnable(2*i + 1) := true.B
|
||
}
|
||
}
|
||
|
||
for( i <- 0 until 16 ){
|
||
when( isWdtSMEnable(i) & (wdtSMCnt(i) < interface.io.cReg.wdtTarCnt(i+1)) ){
|
||
wdtSMCnt(i) := wdtSMCnt(i) + 1.U
|
||
} .elsewhen( ~isWdtSMEnable(i) || (wdtSMCnt(i) >= interface.io.cReg.wdtTarCnt(i+1)) ){
|
||
wdtSMCnt(i) := 0.U
|
||
}
|
||
|
||
// assert( wdtSMCnt(i) <= interface.io.cReg.wdtTarCnt(i+1), s"Assert Failed! wdtSMCnt($i) is larger than wdtTarCnt, Special situation?" )
|
||
|
||
interface.io.wdtTrigger(i+1) := wdtSMCnt(i) === interface.io.cReg.wdtTarCnt(i+1)
|
||
}
|
||
|
||
//看门狗0 发送后回包是否超时
|
||
val isWdtRec2RtnEnable = RegInit(false.B)
|
||
val wdtRec2RtnCnt = Reg(UInt(32.W))
|
||
|
||
when(
|
||
(io.upCDRIn.axis.fire & io.upCDRIn.axis.bits.tlast) |
|
||
~interface.io.cReg.wdtEnable.extract(0)
|
||
){
|
||
isWdtRec2RtnEnable := false.B
|
||
} .elsewhen( ~isWdtRec2RtnEnable & io.downCDROut.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){
|
||
isWdtRec2RtnEnable := true.B
|
||
}
|
||
|
||
when( isWdtRec2RtnEnable & (wdtRec2RtnCnt < interface.io.cReg.wdtTarCnt(0)) ){
|
||
wdtRec2RtnCnt := wdtRec2RtnCnt + 1.U
|
||
} .elsewhen( ~isWdtRec2RtnEnable || (wdtRec2RtnCnt >= interface.io.cReg.wdtTarCnt(0)) ){
|
||
wdtRec2RtnCnt := 0.U
|
||
}
|
||
|
||
// assert( wdtRecCnt < interface.io.cReg.wdtTarCnt(0), "Assert Failed! wdtRecCnt is larger than wdtTarCnt, Special situation?" )
|
||
|
||
interface.io.wdtTrigger(0) := wdtRec2RtnCnt === interface.io.cReg.wdtTarCnt(0)
|
||
|
||
//看门狗17
|
||
val wdtRec2RecCnt = Reg(UInt(32.W))
|
||
|
||
when( interface.io.cReg.wdtEnable.extract(17) & (wdtRec2RecCnt < interface.io.cReg.wdtTarCnt(17)) ){
|
||
wdtRec2RecCnt := wdtRec2RecCnt + 1.U
|
||
} .elsewhen(
|
||
~interface.io.cReg.wdtEnable.extract(17) ||
|
||
io.downCDRIn.axis.fire ||
|
||
(wdtRec2RecCnt >= interface.io.cReg.wdtTarCnt(17))
|
||
){
|
||
wdtRec2RecCnt := 0.U
|
||
}
|
||
|
||
interface.io.wdtTrigger(17) := wdtRec2RecCnt === interface.io.cReg.wdtTarCnt(17)
|
||
|
||
}
|
||
|
||
|
||
|
||
class MstSlvSwitch extends MstSlvSwitchBase
|
||
with MstSlvSwitchMaster
|
||
with MstSlvSwitchSlave
|
||
with MstSlvSwitchWatchDog{
|
||
val isDwUpEx = interface.cReg.dwupEx
|
||
|
||
|
||
when( interface.io.cReg.modeSel === false.B ){ //slave
|
||
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
|
||
io.downCDRIn.serDat := false.B
|
||
io.upCDRIn.serDat := false.B
|
||
when( slaveParser.io.isLoop ){ //回环
|
||
io.dDatOut := false.B
|
||
io.uDatOut := io.dDatIn
|
||
} .otherwise{ //非回环
|
||
io.dDatOut := io.dDatIn
|
||
io.uDatOut := io.uDatIn
|
||
}
|
||
} .otherwise{ //无硬件错误
|
||
when( slaveParser.io.isLoop ){ //回环
|
||
io.downCDRIn.serDat := io.dDatIn
|
||
io.upCDRIn.serDat := io.downCDROut.serDat
|
||
io.dDatOut := false.B
|
||
io.uDatOut := io.upCDROut.serDat
|
||
} .otherwise{ //非回环
|
||
io.downCDRIn.serDat := io.dDatIn
|
||
io.upCDRIn.serDat := io.uDatIn
|
||
io.dDatOut := io.downCDROut.serDat
|
||
io.uDatOut := io.upCDROut.serDat
|
||
}
|
||
}
|
||
} .otherwise{ //master
|
||
io.downCDRIn.serDat := false.B
|
||
io.upCDRIn.serDat := io.uDatIn
|
||
io.dDatOut := io.downCDROut.serDat
|
||
io.uDatOut := false.B
|
||
}
|
||
|
||
|
||
|
||
|
||
}
|