56 lines
1.4 KiB
Plaintext
56 lines
1.4 KiB
Plaintext
.PHONY:com sim clean
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OUTPUT = shin_test
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VCS = vcs -sverilog +v2k -timescale=1ns/1ps \
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-debug_all \
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-full64 \
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-o ${OUTPUT} \
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-l compile.log \
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SIM = ./${OUTPUT} -l run.log
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testShin_vcs:
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python3 ./shinTest/gen_pkt.py
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mkdir -p generated/log
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rm -rf generated/log/*
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${VCS} -f ./shinTest_vcs.f
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${SIM}
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sim:
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${SIM}
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testShin:
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./shinTest/gen_pkt.py
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mkdir -p generated/log
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rm -rf generated/log/*
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iverilog -Wall \
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-o ./generated/shinTest.iverilog \
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-y ./generated/shin \
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-I ./generated/shin \
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-D RANDOMIZE_REG_INIT \
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./shinTest/ShinTopSpiTb.v
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vvp -N ./generated/shinTest.iverilog -lxt2 -fst || true
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./shinTest/check_testcase.py
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testShinClk:
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./shinTest/gen_pkt_clk.py
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mkdir -p generated/log
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rm -rf generated/log/*
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iverilog -Wall \
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-o ./generated/shinTest_clk.iverilog \
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-y ./generated/shin \
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-I ./generated/shin \
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-D RANDOMIZE_REG_INIT \
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./shinTest/ShinTopSpiTb_clk.v
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vvp -N ./generated/shinTest_clk.iverilog -lxt2 -fst|| true
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./shinTest/check_testcase.py
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fstShin:
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gtkwave ./generated/wave.fst 1>/dev/null 2>&1 &
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fstShinClk:
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gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &
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clean:
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rm -rf ./generated/log/* ./generated/shin/*.vh ./generated/shinTest.* ./generated/wave*.*
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