236 lines
7.8 KiB
Makefile
236 lines
7.8 KiB
Makefile
TARGET=riscv64-unknown-elf
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RVCC=$(TARGET)-gcc
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RVCCVERSION=$(shell $(RVCC) --version | grep ^$(RVCC) | sed 's/^.* //g')
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RV32I_MARCH=-march=rv32i -mabi=ilp32
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RV32E_MARCH=-march=rv32e -mabi=ilp32e
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RV32I_CFLAGS=-O2 -D__RV32I_MARCH__
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RV32E_CFLAGS=-O2
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ifeq "$(RVCCVERSION)" "12.2.0"
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RV32I_MARCH=-march=rv32izicsr -mabi=ilp32
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RV32E_MARCH=-march=rv32ezicsr -mabi=ilp32e
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endif
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.PHONY: compile tb wave
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compile:
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rm -rf ./generated/Rtpp
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rm -rf ./rocket-chip/vsim/generated-src/
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mkdir -p ./generated/Rtpp
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cd ./rocket-chip/ && rm -f rocketchip.jar
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cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.RtppConfig
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cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v ./generated/Rtpp/RtppConfig.v
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cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.behav_srams.v ./generated/Rtpp/behav_srams.v
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# sbt "test:runMain test.testModule"
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back:
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rm -f ./generated/back/*
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rm -f ./generated/cdr/*
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sbt "test:runMain test.testModule"
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cp ./src/main/verilog/backBoardMstTop.v ./generated/back/
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cp ./src/main/verilog/oser_rst.v ./generated/back/
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cp ./src/main/verilog/di16_top.v ./generated/back/
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cp ./src/main/verilog/do16_top.v ./generated/back/
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cp ./src/main/verilog/do16inv_top.v ./generated/back/
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cp ./src/main/verilog/qei_top.v ./generated/back/
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cp ./src/main/verilog/spi_top.v ./generated/back/
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cp ./src/main/verilog/defineParam.v ./generated/back/
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ef:
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sbt "test:runMain test.testModule"
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VSimTop:
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rm -rf ./tb/build/
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mkdir -p ./tb/build/
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verilator -Wno-fatal \
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-y ${PWD}/generated/Rtpp/ \
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-y ${PWD}/tb/verilator/ \
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--top-module SimTop \
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--trace-fst \
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--cc ./tb/verilator/SimTop.v \
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--cc ${PWD}/generated/Rtpp/behav_srams.v \
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--cc ${PWD}/generated/Rtpp/RtppConfig.v \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+RANDOMIZE_INVALID_ASSIGN \
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+define+RANDOMIZE_REG_INIT \
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+define+RANDOMIZE_DELAY=0 \
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--exe --build \
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${PWD}/tb/verilator/sim_main.cpp \
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-Mdir ./tb/build/ \
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-j 30
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# +define+RANDOMIZE_MEM_INIT
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test:
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@echo "Start simulation..."
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-./tb/build/VSimTop -w -l -f ./tb/sw/build/mstTest >./tb/sw/build/log.txt 2>&1
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@echo "done! Use the 'make fst' to view the simulation results."
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@echo "Processing simulation log..."
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@cat ./tb/sw/build/log.txt | grep '^\[\ \ 0\]' 1>./tb/sw/build/cpu0_log.txt
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@cat ./tb/sw/build/log.txt | grep '^\[\ \ 1\]' 1>./tb/sw/build/cpu1_log.txt
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@cat ./tb/sw/build/log.txt | grep '^\[\ \ 2\]' 1>./tb/sw/build/cpu2_log.txt
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@cat ./tb/sw/build/log.txt | grep '^\[\ \ 3\]' 1>./tb/sw/build/cpu3_log.txt
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@echo "done! Please check ./tb/sw/build/*log.txt"
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sw:
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rm ./tb/sw/build/* -f
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mkdir -p ./tb/sw/build/
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#这是主站的中断服务程序，以及初始化程序
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$(RVCC) -ggdb $(RV32I_MARCH) $(RV32I_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/tl2cdr \
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-c ./tb/sw/src/mstSvr.S \
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-o ./tb/sw/build/mstSvr.o
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$(RVCC) -ggdb $(RV32I_MARCH) $(RV32I_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
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-T ./tb/sw/linker.lds \
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./tb/sw/build/mstSvr.o \
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-o ./tb/sw/build/mstSvr.elf
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$(TARGET)-objcopy -O binary ./tb/sw/build/mstSvr.elf ./tb/sw/build/mstSvr.bin
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python3 ./tb/sw/bin_2_c_array.py ./tb/sw/build/mstSvr.bin ./tb/sw/build/mstSvr.c
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#这是主站的程序
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$(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/tl2cdr \
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-c ./tb/sw/build/mstSvr.c \
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-o ./tb/sw/build/mstSvr.o
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$(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/tl2cdr \
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-c ./tb/sw/src/mstStartup.S \
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-o ./tb/sw/build/mstStartup.o
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$(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/tl2cdr \
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-c ./tb/sw/tl2cdr/tl2cdr.c \
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-o ./tb/sw/build/tl2cdr.o
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$(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/tl2cdr \
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-c ./tb/sw/src/MstMain.c \
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-o ./tb/sw/build/mstMain.o
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$(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
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-T ./tb/sw/linker.lds \
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./tb/sw/build/mstStartup.o \
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./tb/sw/build/mstMain.o \
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./tb/sw/build/mstSvr.o \
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./tb/sw/build/tl2cdr.o \
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-o ./tb/sw/build/mstTest.elf
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$(TARGET)-objcopy -O binary ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.bin
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$(TARGET)-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/mstTest.elf > ./tb/sw/build/mstTest.dump
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$(TARGET)-objcopy -O verilog ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.verilog
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sed -i 's/@400/@000/g' ./tb/sw/build/mstTest.verilog
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#这是从站的中断服务程序，以及初始化程序
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$(RVCC) -ggdb $(RV32I_MARCH) $(RV32I_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/tl2cdr \
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-c ./tb/sw/src/slvSvr.S \
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-o ./tb/sw/build/slvSvr.o
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$(RVCC) -ggdb $(RV32I_MARCH) $(RV32I_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
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-T ./tb/sw/linker.lds \
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./tb/sw/build/slvSvr.o \
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-o ./tb/sw/build/slvSvr.elf
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$(TARGET)-objcopy -O binary ./tb/sw/build/slvSvr.elf ./tb/sw/build/slvSvr.bin
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python3 ./tb/sw/bin_2_c_array.py ./tb/sw/build/slvSvr.bin ./tb/sw/build/slvSvr.c
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#这是从站的程序
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$(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/tl2cdr \
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-c ./tb/sw/build/slvSvr.c \
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-o ./tb/sw/build/slvSvr.o
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$(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/tl2cdr \
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-c ./tb/sw/tl2cdr/tl2cdr.c \
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-o ./tb/sw/build/tl2cdr.o
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$(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/tl2cdr \
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-c ./tb/sw/src/SlvMain.c \
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-o ./tb/sw/build/slvMain.o
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$(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
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-I ./tb/sw/ -I ./tb/sw/src \
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-I ./tb/sw/tl2cdr \
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-c ./tb/sw/src/slvStartup.S \
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-o ./tb/sw/build/slvStartup.o
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$(RVCC) -ggdb $(RV32E_MARCH) $(RV32E_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
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-T ./tb/sw/linker.lds \
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./tb/sw/build/slvSvr.o \
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./tb/sw/build/slvStartup.o \
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./tb/sw/build/slvMain.o \
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./tb/sw/build/tl2cdr.o \
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-o ./tb/sw/build/slvTest.elf
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$(TARGET)-objcopy -O binary ./tb/sw/build/slvTest.elf ./tb/sw/build/slvTest.bin
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$(TARGET)-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/slvTest.elf > ./tb/sw/build/slvTest.dump
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$(TARGET)-objcopy -O verilog ./tb/sw/build/slvTest.elf ./tb/sw/build/slvTest.verilog
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sed -i 's/@400/@000/g' ./tb/sw/build/slvTest.verilog
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python3 ./tb/sw/bin_to_hex.py
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python3 ./tb/sw/bin_to_coe.py
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fst:
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gtkwave ./tb/build/wave.fst &
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VSimBack:
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rm -rf ./tb/build/
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mkdir -p ./tb/build/
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verilator -Wno-fatal \
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--timescale "1 ns / 1 ps" \
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-y ${PWD}/tb/ \
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-y ${PWD}/generated/ \
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--top-module BackPlaneChainTest \
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--trace-fst \
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--cc ./generated/BackPlaneChainTest.v \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+RANDOMIZE_INVALID_ASSIGN \
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+define+RANDOMIZE_REG_INIT \
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+define+RANDOMIZE_MEM_INIT \
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+define+RANDOMIZE_DELAY=0 \
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--exe --build \
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${PWD}/tb/sim_backChain.cpp \
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-Mdir ./tb/build/ \
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-j 30
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tb:
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iverilog -Wall \
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-o ./build/wave.iverilog \
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-y ./tb \
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-y ./generated/cdr/ \
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-I ./tb \
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-I ./generated/cdr/ \
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-D RANDOMIZE_REG_INIT \
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./tb/backSys_tb.v
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vvp -N ./build/wave.iverilog -lxt2
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vcd:
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gtkwave ./build/wave.vcd &
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