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31b362b291217393fbd5d75532e4438ecfa8d88e
eb001/Makefile

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Makefile
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TARGET=riscv64-unknown-elf
RVCC=$(TARGET)-gcc
RVCCVERSION=$(shell $(RVCC) --version | grep ^$(RVCC) | sed 's/^.* //g')
ISR_MARCH=-march=rv32i -mabi=ilp32
APP_MARCH=-march=rv32i -mabi=ilp32
ISR_CFLAGS=-O2
APP_CFLAGS=-O2
ifeq "$(RVCCVERSION)" "12.2.0"
ISR_MARCH=-march=rv32izicsr -mabi=ilp32
APP_MARCH=-march=rv32izicsr -mabi=ilp32
endif
.PHONY: compile tb wave
compile:
rm -rf ./generated/Rtpp
rm -rf ./rocket-chip/vsim/generated-src/
mkdir -p ./generated/Rtpp
cd ./rocket-chip/ && rm -f rocketchip.jar
cd ./rocket-chip/vsim && make verilog CONFIG=freechips.rocketchip.system.RtppConfig
sed -e "s/CoreID = _RAND/\/\/CoreID = _RAND/g" ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v > ./generated/Rtpp/RtppConfig.v
# cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.v ./generated/Rtpp/RtppConfig.v
cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig.behav_srams.v ./generated/Rtpp/behav_srams.v
cp ./rocket-chip/vsim/generated-src/freechips.rocketchip.system.RtppConfig/MirrorSRAMDP.v ./generated/Rtpp/MirrorSRAMDP.v
# sbt "test:runMain test.testModule"
back:
rm -f ./generated/back/*
rm -f ./generated/cdr/*
sbt "test:runMain test.testModule"
cp ./src/main/verilog/backBoardMstTop.v ./generated/back/
cp ./src/main/verilog/oser_rst.v ./generated/back/
cp ./src/main/verilog/di16_top.v ./generated/back/
cp ./src/main/verilog/do16c_top.v ./generated/back/
cp ./src/main/verilog/do16p_top.v ./generated/back/
cp ./src/main/verilog/spi_top.v ./generated/back/
cp ./src/main/verilog/defineParam.v ./generated/back/
shin:
rm -f ./generated/shin/*
sbt "test:runMain test.testShinModule"
testShin:
python3 ./tb/shinTest/gen_pkt.py
mkdir -p generated/log
rm -rf generated/log/*
iverilog -Wall \
-o ./tb/build/shinTest.iverilog \
-y ./generated/shin \
-I ./generated/shin \
-D RANDOMIZE_REG_INIT \
-D IVERILOG_COMPILE \
./tb/shinTest/ShinTopSpiTb.v
vvp -N ./tb/build/shinTest.iverilog -lxt2 -fst || true
python3 ./tb/shinTest/check_testcase.py
testShinClk:
python3 ./tb/shinTest/gen_pkt_clk.py --dev1 0 200
mkdir -p generated/log
rm -rf generated/log/*
iverilog -Wall \
-o ./tb/build/shinTest_clk.iverilog \
-y ./generated/shin \
-I ./generated/shin \
-D RANDOMIZE_REG_INIT \
-D IVERILOG_COMPILE \
./tb/shinTest/ShinTopSpiTb_clk.v
vvp -N ./tb/build/shinTest_clk.iverilog -lxt2 -fst || true
python3 ./tb/shinTest/check_testcase.py
testCDR:
iverilog -Wall \
-o ./tb/build/simCDR.iverilog \
-y ./generated/shin \
-y ./generated/SimCDR \
-I ./generated/SimCDR \
-I ./generated/shin \
-D RANDOMIZE_REG_INIT \
-D IVERILOG_COMPILE \
./tb/shinTest/SimCDRTb.v
vvp -N ./tb/build/simCDR.iverilog -lxt2 -fst
testFilter:
./tb/shinTest/test_filter.py
vcdFilter:
gtkwave ./tb/build/test_filter.vcd 1>/dev/null 2>&1 &
fstShin:
gtkwave ./generated/wave.fst 1>/dev/null 2>&1 &
fstShinClk:
gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &
ef:
sbt "test:runMain test.testModule"
VSimTop:
rm -rf ./tb/build/
mkdir -p ./tb/build/
verilator -Wno-fatal \
-y ${PWD}/generated/Rtpp/ \
-y ${PWD}/tb/verilator/ \
--top-module SimTop \
--trace \
--trace-fst \
--cc ./tb/verilator/SimTop.v \
--cc ${PWD}/generated/Rtpp/behav_srams.v \
--cc ${PWD}/generated/Rtpp/RtppConfig.v \
--cc ${PWD}/generated/Rtpp/MirrorSRAMDP.v \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+RANDOMIZE_INVALID_ASSIGN \
+define+RANDOMIZE_REG_INIT \
+define+RANDOMIZE_DELAY=0 \
--exe --build \
${PWD}/tb/verilator/sim_main.cpp \
-Mdir ./tb/build/ \
-j 30
# +define+RANDOMIZE_MEM_INIT
test:
@echo "Start simulation..."
-./tb/build/VSimTop -w -l -f ./tb/sw/build/mstTest >./tb/sw/build/log.txt 2>&1
@echo "done! Use the 'make fst' to view the simulation results."
@echo "Processing simulation log..."
@cat ./tb/sw/build/log.txt | grep '^\[\ \ 0\]' 1>./tb/sw/build/cpu0_log.txt
@cat ./tb/sw/build/log.txt | grep '^\[\ \ 1\]' 1>./tb/sw/build/cpu1_log.txt
@cat ./tb/sw/build/log.txt | grep '^\[\ \ 2\]' 1>./tb/sw/build/cpu2_log.txt
@cat ./tb/sw/build/log.txt | grep '^\[\ \ 3\]' 1>./tb/sw/build/cpu3_log.txt
@echo "done! Please check ./tb/sw/build/*log.txt"
sw:
rm ./tb/sw/build/* -f
mkdir -p ./tb/sw/build/
#这是主站的中断服务程序，以及初始化程序
$(RVCC) -ggdb $(ISR_MARCH) $(ISR_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/src/hlmSvrOpt.S \
-o ./tb/sw/build/hlmSvrOpt.o
$(RVCC) -ggdb $(ISR_MARCH) $(ISR_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
-T ./tb/sw/linker.lds \
./tb/sw/build/hlmSvrOpt.o \
-o ./tb/sw/build/hlmSvrOpt.elf
$(TARGET)-objcopy -O binary ./tb/sw/build/hlmSvrOpt.elf ./tb/sw/build/hlmSvrOpt.bin
python3 ./tb/sw/bin_2_c_array.py ./tb/sw/build/hlmSvrOpt.bin ./tb/sw/build/hlmSvrOpt.c
#这是主站的程序
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/build/hlmSvrOpt.c \
-o ./tb/sw/build/hlmSvrOpt.o
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/src/mstStartup.S \
-o ./tb/sw/build/mstStartup.o
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/src/clint.c \
-o ./tb/sw/build/clint.o
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/src/halfLvdsMacSvr.c \
-o ./tb/sw/build/halfLvdsMacSvr.o
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/src/plic.c \
-o ./tb/sw/build/plic.o
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/tl2cdr/tl2cdr.c \
-o ./tb/sw/build/tl2cdr.o
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/src/MstMain.c \
-o ./tb/sw/build/mstMain.o
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
-T ./tb/sw/linker.lds \
./tb/sw/build/mstStartup.o \
./tb/sw/build/mstMain.o \
./tb/sw/build/hlmSvrOpt.o \
./tb/sw/build/tl2cdr.o \
./tb/sw/build/halfLvdsMacSvr.o \
./tb/sw/build/plic.o \
./tb/sw/build/clint.o \
-o ./tb/sw/build/mstTest.elf
$(TARGET)-objcopy -O binary ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.bin
$(TARGET)-objdump --disassemble-all -S --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/mstTest.elf > ./tb/sw/build/mstTest.dump
$(TARGET)-objcopy -O verilog ./tb/sw/build/mstTest.elf ./tb/sw/build/mstTest.verilog
sed -i 's/@400/@000/g' ./tb/sw/build/mstTest.verilog
#这是从站的中断服务程序，以及初始化程序
#$(RVCC) -ggdb $(ISR_MARCH) $(ISR_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
#-I ./tb/sw/ -I ./tb/sw/src \
#-I ./tb/sw/tl2cdr \
#-c ./tb/sw/src/slvSvr.S \
#-o ./tb/sw/build/slvSvr.o
#$(RVCC) -ggdb $(ISR_MARCH) $(ISR_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
#-T ./tb/sw/linker.lds \
#./tb/sw/build/slvSvr.o \
#-o ./tb/sw/build/slvSvr.elf
#$(TARGET)-objcopy -O binary ./tb/sw/build/slvSvr.elf ./tb/sw/build/slvSvr.bin
#python3 ./tb/sw/bin_2_c_array.py ./tb/sw/build/slvSvr.bin ./tb/sw/build/slvSvr.c
#这是从站的程序
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/build/hlmSvrOpt.c \
-o ./tb/sw/build/hlmSvrOpt.o
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/tl2cdr/tl2cdr.c \
-o ./tb/sw/build/tl2cdr.o
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/src/clint.c \
-o ./tb/sw/build/clint.o
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/src/halfLvdsMacSvr.c \
-o ./tb/sw/build/halfLvdsMacSvr.o
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/src/plic.c \
-o ./tb/sw/build/plic.o
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/src/SlvMain.c \
-o ./tb/sw/build/slvMain.o
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-I ./tb/sw/tl2cdr \
-c ./tb/sw/src/slvStartup.S \
-o ./tb/sw/build/slvStartup.o
$(RVCC) -ggdb $(APP_MARCH) $(APP_CFLAGS) -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
-T ./tb/sw/linker.lds \
./tb/sw/build/hlmSvrOpt.o \
./tb/sw/build/slvStartup.o \
./tb/sw/build/slvMain.o \
./tb/sw/build/tl2cdr.o \
./tb/sw/build/halfLvdsMacSvr.o \
./tb/sw/build/plic.o \
./tb/sw/build/clint.o \
-o ./tb/sw/build/slvTest.elf
$(TARGET)-objcopy -O binary ./tb/sw/build/slvTest.elf ./tb/sw/build/slvTest.bin
$(TARGET)-objdump -S --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data --section=.bss --section=.rodata --section=.trap_entry ./tb/sw/build/slvTest.elf > ./tb/sw/build/slvTest.dump
$(TARGET)-objcopy -O verilog ./tb/sw/build/slvTest.elf ./tb/sw/build/slvTest.verilog
sed -i 's/@400/@000/g' ./tb/sw/build/slvTest.verilog
python3 ./tb/sw/bin_to_hex.py
python3 ./tb/sw/bin_to_coe.py
$(TARGET)-size ./tb/sw/build/mstTest.elf
$(TARGET)-size ./tb/sw/build/slvTest.elf
fst:
gtkwave ./tb/build/wave.fst &
debug_hlm:
gtkwave -S ./tb/sw/src/view_signal.tcl ./tb/build/wave.fst 1>/dev/null 2>&1 &
VSimBack:
rm -rf ./tb/build/
mkdir -p ./tb/build/
verilator -Wno-fatal \
--timescale "1 ns / 1 ps" \
-y ${PWD}/tb/ \
-y ${PWD}/generated/ \
--top-module BackPlaneChainTest \
--trace-fst \
--cc ./generated/BackPlaneChainTest.v \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+RANDOMIZE_INVALID_ASSIGN \
+define+RANDOMIZE_REG_INIT \
+define+RANDOMIZE_MEM_INIT \
+define+RANDOMIZE_DELAY=0 \
--exe --build \
${PWD}/tb/sim_backChain.cpp \
-Mdir ./tb/build/ \
-j 30
# tb:
# iverilog -Wall \
# -o ./build/wave.iverilog \
# -y ./tb \
# -y ./generated/cdr/ \
# -I ./tb \
# -I ./generated/cdr/ \
# -D RANDOMIZE_REG_INIT \
# ./tb/backSys_tb.v
# vvp -N ./build/wave.iverilog -lxt2
# vcd:
# gtkwave ./build/wave.vcd &
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