59 lines
1.3 KiB
Scala
59 lines
1.3 KiB
Scala
package MAC
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import chisel3._
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import chisel3.util._
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class MacSRAMIO extends Bundle{
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val we = Input(Vec(4, Bool())) // Write enable input, active high
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val oe = Input(Bool()) // Output enable input, active high
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val addr = Input(UInt(8.W)) // address bus inputs
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val di = Input(UInt(32.W)) // input data bus
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val dato = Output(UInt(32.W)) // output data bus
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}
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class MacSRAM extends Module{
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val io: MacSRAMIO = IO(new MacSRAMIO)
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// Generic RAM's registers and wires
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val mem0 = Mem( 256, UInt(8.W) )
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val mem1 = Mem( 256, UInt(8.W) )
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val mem2 = Mem( 256, UInt(8.W) )
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val mem3 = Mem( 256, UInt(8.W) )
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val q = Wire(UInt(32.W))
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val raddr = Reg( UInt(8.W) )
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// Data output drivers
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io.dato := Mux((io.oe), q, DontCare)
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// read operation
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when( true.B ){
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raddr := io.addr // read address needs to be registered to read clock
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}
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q := Mux(reset.asBool, 0.U, Cat(mem3.read(raddr), mem2.read(raddr), mem1.read(raddr), mem0.read(raddr)))
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// write operation
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when(io.we(3)){
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mem3.write(io.addr, io.di(31,24))
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}
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when(io.we(2)){
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mem2.write(io.addr, io.di(23,16))
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}
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when(io.we(1)){
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mem1.write(io.addr, io.di(15, 8))
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}
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when(io.we(0)){
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mem0.write(io.addr, io.di( 7, 0))
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}
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}
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