160 lines
4.1 KiB
Plaintext
160 lines
4.1 KiB
Plaintext
package Switch
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import chisel3._
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import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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abstract class SwitchMuxBase(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule{
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class MacTileLinkMasterIO extends Bundle{
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val A = Decoupled(new TLBundleA(edgeOut.bundle))
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val D = Flipped(Decoupled(new TLBundleD(edgeOut.bundle)))
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}
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class SwitchMuxIO(implicit p: Parameters) extends SwitchBundle{
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val dmaMst = new MacTileLinkMasterIO
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val triTx = Input(Bool())
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val triRx = Output(Bool())
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val r_TxPtr = Input(UInt(32.W))
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val r_RxPtr = Input(UInt(32.W))
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val r_TxLen = Input(UInt(16.W))
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val r_RxLen = Output(UInt(16.W))
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val rxEnq = Vec(chn, Flipped(new Receive_Enq_Bundle))
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val txDeq = Vec(chn, new Transmit_Bundle)
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}
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val io: SwitchMuxIO = IO(new SwitchMuxIO)
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val (_, _, isLastD, transDCnt) = edgeOut.count(io.dmaMst.D)
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val rxBuff = Module(new RxBuff)
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rxBuff.io.enq <> io.rxEnq(0)
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val txBuff = Module(new TxBuff)
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txBuff.io.deq <> io.txDeq(0)
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def stateIdle = 0.U
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def stateRx = 1.U
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def stateTx = 2.U
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val stateNxt = Wire(UInt(2.W))
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val stateCur = RegNext(stateNxt, stateIdle)
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val stateDMA = RegInit(0.U(2.W))
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when( stateNxt =/= stateIdle && stateCur === stateIdle ){
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stateDMA := 1.U
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} .elsewhen( io.dmaMst.A.fire ){
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stateDMA := 2.U
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} .elsewhen( io.dmaMst.D.fire & isLastD ){
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when( stateCur === stateTx & dmaAddress < (io.r_TxPtr + io.r_TxLen) ){
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stateDMA := 0.U
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} .elsewhen( stateCur === stateRx & rxBuff.io.deq.data.valid ){
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stateDMA := 0.U
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} .otherwise{
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stateDMA := 1.U
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}
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}
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stateNxt :=
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Mux1H(Seq(
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( stateCur === stateIdle ) -> Mux( (io.triTx & io.r_TxLen > 32.U), stateTx, Mux( rxBuff.io.deq.header.fire, stateRx, stateIdle ) ),
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( stateCur === stateRx ) -> Mux( rxBuff.io.deq.ctrl.fire, stateIdle, stateRx ),
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( stateCur === stateTx ) -> Mux( txBuff.io.enq.resp.fire, stateIdle, stateTx ),
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))
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io.triRx := rxBuff.io.deq.ctrl.fire
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io.r_RxLen := RegEnable( rxBuff.io.deq.ctrl.bits.LatchedRxLength, rxBuff.io.deq.ctrl.fire )
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rxBuff.io.deq.ctrl.ready := stateCur === stateRx & io.dmaMst.D.fire & isLastD
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txBuff.io.enq.resp.ready := true.B
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val dmaAValid = RegInit(false.B)
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val dmaABits = Reg(new TLBundleA(edgeOut.bundle))
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val dmaAddress = Reg( UInt(32.W) )
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when( stateCur === stateIdle & stateNxt === stateTx ){
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dmaAddress := io.r_TxPtr
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} .elsewhen( stateCur === stateIdle & stateNxt === stateRx ){
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dmaAddress := io.r_RxPtr
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} .elsewhen( io.dmaMst.A.fire ){
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dmaAddress := dmaAddress + 1.U
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}
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rxBuff.io.deq.data.ready := io.dmaMst.A.fire & (stateCur === stateRx)
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assert( ~(rxBuff.io.deq.data.ready & ~rxBuff.io.deq.data.valid) )
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rxBuff.io.deq.header.ready := ~(io.triTx & io.r_TxLen > 32.U) & stateCur === stateIdle
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when( io.dmaMst.A.fire ){
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dmaAValid := false.B
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}.elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateTx ){
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dmaAValid := true.B
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dmaABits :=
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edgeOut.Get(
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fromSource = 0.U,
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toAddress = dmaAddress,
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lgSize = log2Ceil(8/8).U,
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)._2
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} .elsewhen( stateDMA === 1.U & ~io.dmaMst.A.valid & stateCur === stateRx ) {
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dmaAValid := true.B
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dmaABits :=
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edgeOut.Put(
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fromSource = 0.U,
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toAddress = dmaAddress,
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lgSize = log2Ceil(8/8).U,
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data = rxBuff.io.deq.data.bits,
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mask = "b1".U,
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)._2
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}
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io.dmaMst.A.valid := dmaAValid
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io.dmaMst.A.bits := dmaABits
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txBuff.io.enq.req.valid := io.dmaMst.D.valid & stateCur === stateTx
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txBuff.io.enq.req.bits.data := io.dmaMst.D.bits.data
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txBuff.io.enq.req.bits.isStart := dmaAddress === io.r_TxPtr
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txBuff.io.enq.req.bits.isLast := dmaAddress === (io.r_TxPtr + io.r_TxLen)
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io.dmaMst.D.ready :=
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Mux1H(Seq(
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( stateCur === stateRx ) -> true.B,
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( stateCur === stateTx ) -> txBuff.io.enq.req.ready,
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))
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}
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trait SwitchMuxDMATx{ this: SwitchMuxBase =>
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}
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class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchMuxBase(TLEdgeOut)
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with SwitchMuxDMATx
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