192 lines
4.5 KiB
Verilog
192 lines
4.5 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2025/05/13 11:43:33
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// Design Name:
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// Module Name: FPGATop
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module FPGATop(
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input clkin,
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input resetIn,
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input dDatIn_p,
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input dDatIn_n,
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output dDatOut_p,
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output dDatOut_n,
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input uDatIn_p,
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input uDatIn_n,
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output uDatOut_p,
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output uDatOut_n,
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input sck,
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input mosi,
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output miso,
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input csn,
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input io_iqspi_sck,
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inout [3:0] io_iqspi_data,
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input io_iqspi_csn,
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output interrupt,
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output [3:0] io_led
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);
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wire clk50M;
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wire clk400M;
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wire reset;
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wire dDatIn;
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wire dDatOut;
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wire uDatIn;
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wire uDatOut;
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clk_wiz_0 i_clk
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(
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// Clock out ports
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.clk_out1(clk50M),
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.clk_out2(clk400M),
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// Clock in ports
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.clk_in1(clkin)
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);
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// proc_sys_reset_0 i_proc_sys_reset(
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// .slowest_sync_clk(clk50M),
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// .ext_reset_in(resetIn),
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// .aux_reset_in(1'b0),
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// .mb_debug_sys_rst(1'b0),
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// .dcm_locked(1'b1),
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// .mb_reset(),
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// .bus_struct_reset(),
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// .peripheral_reset(reset),
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// .interconnect_aresetn(),
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// .peripheral_aresetn()
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// );
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assign reset = resetIn;
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wire [3:0] iqspi_mosi;
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wire [3:0] iqspi_miso;
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wire iqspi_isDirIn;
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wire isSoftReset;
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wire [7:0] led;
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ShinTop i_ShinTop(
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.clock(clk50M),
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.reset(reset),//|isSoftReset),
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.io_clk8x(clk400M),
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.io_dDatIn(dDatIn),
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.io_dDatOut(dDatOut),
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.io_uDatIn(uDatIn),
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.io_uDatOut(uDatOut),
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.io_ospi_sck(sck),
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.io_ospi_mosi(mosi),
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.io_ospi_miso(miso),
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.io_ospi_csn(csn),
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.io_interrupt(interrupt),
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.io_rsp_bits_isError(),
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.io_iqspi_sck(io_iqspi_sck),
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.io_iqspi_mosi(iqspi_mosi),
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.io_iqspi_miso(iqspi_miso),
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.io_iqspi_isDirIn(iqspi_isDirIn),
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.io_iqspi_csn(io_iqspi_csn),
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.io_oqspi_sck(1'b0),
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.io_oqspi_mosi(4'b0),
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.io_oqspi_miso(),
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.io_oqspi_isDirIn(),
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.io_oqspi_csn(1'b1),
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.io_iSync_0(),
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.io_iSync_1(),
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.io_iSync_2(),
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.io_iSync_3(),
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.io_oSync_0(),
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.io_oSync_1(),
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.io_oSync_2(),
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.io_oSync_3(),
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.io_isSoftReset(isSoftReset),
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.io_ledTest(led),
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.io_latchPin_0(),
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.io_latchPin_1()
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);
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assign io_led = led[5:2];
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IOBUF QSPI_D0_inst (
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.O(iqspi_mosi[0]), // Buffer output
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.IO(io_iqspi_data[0]), // Buffer inout port (connect directly to top-level port)
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.I(iqspi_miso[0]), // Buffer input
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.T(iqspi_isDirIn) // 3-state enable input, high=input, low=output
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);
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IOBUF QSPI_D1_inst (
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.O(iqspi_mosi[1]), // Buffer output
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.IO(io_iqspi_data[1]), // Buffer inout port (connect directly to top-level port)
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.I(iqspi_miso[1]), // Buffer input
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.T(iqspi_isDirIn) // 3-state enable input, high=input, low=output
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);
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IOBUF QSPI_D2_inst (
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.O(iqspi_mosi[2]), // Buffer output
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.IO(io_iqspi_data[2]), // Buffer inout port (connect directly to top-level port)
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.I(iqspi_miso[2]), // Buffer input
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.T(iqspi_isDirIn) // 3-state enable input, high=input, low=output
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);
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IOBUF QSPI_D3_inst (
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.O(iqspi_mosi[3]), // Buffer output
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.IO(io_iqspi_data[3]), // Buffer inout port (connect directly to top-level port)
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.I(iqspi_miso[3]), // Buffer input
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.T(iqspi_isDirIn) // 3-state enable input, high=input, low=output
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);
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IBUFDS i_dDatIn (
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.O(dDatIn), // Buffer output
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.I(dDatIn_p), // Diff_p buffer input (connect directly to top-level port)
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.IB(dDatIn_n) // Diff_n buffer input (connect directly to top-level port)
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);
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IBUFDS i_uDatIn (
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.O(uDatIn), // Buffer output
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.I(uDatIn_p), // Diff_p buffer input (connect directly to top-level port)
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.IB(uDatIn_n) // Diff_n buffer input (connect directly to top-level port)
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);
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OBUFDS i_dDatOut (
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.O(dDatOut_p), // Diff_p output (connect directly to top-level port)
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.OB(dDatOut_n), // Diff_n output (connect directly to top-level port)
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.I(dDatOut) // Buffer input
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);
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OBUFDS i_uDatOut (
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.O(uDatOut_p), // Diff_p output (connect directly to top-level port)
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.OB(uDatOut_n), // Diff_n output (connect directly to top-level port)
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.I(uDatOut) // Buffer input
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);
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endmodule
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