116 lines
3.0 KiB
Scala
116 lines
3.0 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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trait BackBoardSlvOut16{ this: BackBoardSlvLocal =>
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val outRegSync = Wire(UInt(16.W))
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val mthodReg = RegInit(0.U(16.W))
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val valueReg = RegInit(0.U(16.W))
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val outPin = Wire(UInt(16.W))
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outPin :=
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Mux(statusPR === 3.U, outRegSync, (mthodReg & valueReg) | (~mthodReg & outRegSync))
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}
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trait DoutInspect{ this: BackBoardSlvLocal =>
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val flt = IO(Input(Vec(2, Bool())))
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val v24Det = IO(Input(Bool()))
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val LED_ERR = IO(Output(Bool()))
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LED_ERR := ~RegNext(~v24Det)
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when( statusPage === 0.U ){
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upReg(2) := Cat( 0.U(7.W), RegNext(~v24Det) )
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upReg(3) := 0.U
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upReg(4) := Cat( 0.U(7.W), RegNext(~flt(0)) )
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upReg(5) := 0.U
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upReg(6) := Cat( 0.U(7.W), RegNext(~flt(1)) )
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upReg(7) := 0.U
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}
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}
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trait DoutInspect_Plus{ this: BackBoardSlvLocal =>
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val flashCounter: UInt
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val v24Det = IO(Input(Bool()))
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val LED_ERR = IO(Output(Bool()))
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val fin_cur = IO(Input(UInt(4.W)))
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val fin_sel = IO(Output(UInt(3.W)))
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val fin_clk = IO(Output(Bool()))
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val fin_vol = IO(Input(UInt(3.W)))
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val inspectCurr = for( i <- 0 until 4 ) yield { RegInit(0.U(8.W)) }
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val finSelReg = RegInit(0.U(3.W)); fin_sel := finSelReg
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val finClkReg = RegInit(false.B); fin_clk := finClkReg
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when(flashCounter(2,0).andR){
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finClkReg := ~finClkReg
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}
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when( flashCounter(2,0).andR & finClkReg ){
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finSelReg := finSelReg + 1.U
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inspectCurr(0) := ( inspectCurr(0) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(0) << finSelReg )
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inspectCurr(1) := ( inspectCurr(1) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(1) << finSelReg )
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inspectCurr(2) := ( inspectCurr(2) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(2) << finSelReg )
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inspectCurr(3) := ( inspectCurr(3) & ~( 1.U(8.W) << finSelReg) ) | ( fin_cur.extract(3) << finSelReg )
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}
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LED_ERR := ~( RegNext(~v24Det) | ( inspectCurr.map{ (isp: UInt) => (isp =/= 0.U) }.reduce(_|_) ) | ( RegNext(fin_vol) =/= 0.U ) )
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when( statusPage === 0.U ){
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upReg(2) := Cat( 0.U(4.W), RegNext(fin_vol), RegNext(~v24Det) )
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upReg(3) := 0.U
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upReg(4) := inspectCurr(0)
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upReg(5) := inspectCurr(1)
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upReg(6) := inspectCurr(2)
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upReg(7) := inspectCurr(3)
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}
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}
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abstract class DOut16 extends BackBoardSlvLocal
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with BackBoardSlvStatusPR
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with BackBoardSlvOut16{
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val out = IO(Output(UInt(16.W)))
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val outReg = RegInit(0.U(16.W))
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when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
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outReg := Cat(downRegTemp(13), downRegTemp(12))
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}
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when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
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mthodReg := Cat(downRegTemp(9), downRegTemp(8))
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valueReg := Cat(downRegTemp(11), downRegTemp(10))
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}
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outRegSync := RegEnable( outReg, 0.U, isUpdate )
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when( statusPage === 0.U ){
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upReg(8) := mthodReg(7,0)
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upReg(9) := mthodReg(15,8)
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upReg(10) := valueReg(7,0)
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upReg(11) := valueReg(15,8)
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upReg(12) := outReg(7,0)
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upReg(13) := outReg(15,8)
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}
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out := ~outPin
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}
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class DOut16c extends DOut16 with DoutInspect
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class DOut16p extends DOut16 with DoutInspect_Plus
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