335 lines
7.8 KiB
Scala
335 lines
7.8 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline {
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class MirrorSRAMDownIO extends Bundle{
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val addrr = Input(UInt(11.W))
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val addrw = Input(UInt(10.W))
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val dataw = Input( UInt(16.W) )
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val datar = Output( UInt(8.W) )
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val enw = Input(Bool())
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val enr = Input(Bool())
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val clockr = Input(Bool())
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val clockw = Input(Bool())
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}
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val io: MirrorSRAMDownIO = IO(new MirrorSRAMDownIO)
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setInline("MirrorSRAMDown.v",
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"""
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| module MirrorSRAMDown(
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| input [15:0] dataw,
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| input [9:0] addrw,
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| input enw,
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| output [7:0] datar,
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| input [10:0] addrr,
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| input enr,
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| input clockr,
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| input clockw
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| );
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| reg [15:0] ram[0:1023];
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| reg [7:0] data_r_reg;
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| always @(posedge clockw) begin
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| if(enw) begin
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| ram[addrw] <= #1 dataw;
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| end
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| end
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| always @(posedge clockr) begin
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| if(enr) begin
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| data_r_reg <= #1 addrr[0] ? ram[addrr[10:1]][15:8] : ram[addrr[10:1]][7:0];
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| end
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| end
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| assign datar = data_r_reg;
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| initial begin
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| for ( integer i = 0; i < 1024; i = i + 1 ) begin
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| ram[i] = $random;
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| end
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| data_r_reg = $random;
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| end
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|endmodule
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""".stripMargin)
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}
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class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
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class MirrorSRAMUpIO extends Bundle{
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val addrr = Input(UInt(10.W))
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val addrw = Input(UInt(11.W))
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val dataw = Input( UInt(8.W) )
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val datar = Output( UInt(16.W) )
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val enw = Input(Bool())
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val enr = Input(Bool())
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val clockr = Input(Bool())
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val clockw = Input(Bool())
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}
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val io: MirrorSRAMUpIO = IO(new MirrorSRAMUpIO)
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setInline("MirrorSRAMUp.v",
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"""
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| module MirrorSRAMUp(
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| input [7:0] dataw,
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| input [10:0] addrw,
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| input enw,
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| output [15:0] datar,
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| input [9:0] addrr,
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| input enr,
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| input clockr,
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| input clockw
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| );
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| reg [7:0] ram[0:2047] /* synthesis syn_ramstyle="block_ram" */;
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| reg [15:0] data_r_reg;
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| always @(posedge clockw) begin
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| if(enw) begin
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| ram[addrw] <= #1 dataw;
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| end
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| end
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| always @(posedge clockr) begin
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| if(enr) begin
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| data_r_reg <= #1 { ram[2*addrr+1], ram[2*addrr] };
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| end
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| end
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| assign datar = data_r_reg;
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|endmodule
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""".stripMargin)
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}
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class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {
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class MirrorSRAMDPIO extends Bundle{
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val addrA = Input(UInt(10.W))
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val datawA = Input( UInt(16.W) )
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val datarA = Output( UInt(16.W) )
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val enwA = Input(Bool())
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val enrA = Input(Bool())
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val clockA = Input(Bool())
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val addrB = Input(UInt(10.W))
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val datawB = Input( UInt(16.W) )
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val datarB = Output( UInt(16.W) )
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val enwB = Input(Bool())
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val enrB = Input(Bool())
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val clockB = Input(Bool())
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}
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val io: MirrorSRAMDPIO = IO(new MirrorSRAMDPIO)
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setInline("MirrorSRAMDP.v",
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"""
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| module MirrorSRAMDP(
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| input [15:0] datawA,
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| input [9:0] addrA,
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| input enwA,
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| input enrA,
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| output [15:0] datarA,
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| input clockA,
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| input [15:0] datawB,
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| input [9:0] addrB,
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| input enwB,
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| input enrB,
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| output [15:0] datarB,
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| input clockB
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| );
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| reg [15:0] mem[0:1023];
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| reg [15:0] data_outa_reg = 16'b0;
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| reg [15:0] data_outb_reg = 16'b0;
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| assign datarA = data_outa_reg;
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| assign datarB = data_outb_reg;
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| always@( posedge clockA ) begin
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| if( enrA ) begin
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| end
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| if( enwA ) begin
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| mem[addrA] <= datawA;
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| end else begin
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| data_outa_reg <= mem[addrA];
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| end
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| end
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| always@( posedge clockB ) begin
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| if(enrB) begin
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| end
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| if( enwB ) begin
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| mem[addrB] <= datawB;
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| end else begin
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| data_outb_reg <= mem[addrB];
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| end
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| end
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| initial begin
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| for( integer i = 0; i < 1024; i = i + 1 ) begin
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| mem[i] = $random;
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| end
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| end
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| //Gowin_DPB your_instance_name(
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| // .douta(datarA), //output [15:0] douta
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| // .doutb(datarB), //output [15:0] doutb
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| // .clka(clockA), //input clka
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| // .ocea(1'b1), //input ocea
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| // .cea(1'b1), //input cea
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| // .reseta(1'b0), //input reseta
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| // .wrea(enwA), //input wrea
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| // .clkb(clockB), //input clkb
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| // .oceb(1'b1), //input oceb
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| // .ceb(1'b1), //input ceb
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| // .resetb(1'b0), //input resetb
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| // .wreb(enwB), //input wreb
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| // .ada(addrA), //input [3:0] ada
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| // .dina(datawA), //input [15:0] dina
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| // .adb(addrB), //input [3:0] adb
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| // .dinb(datawB) //input [15:0] dinb
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| //);
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|endmodule
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""".stripMargin)
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}
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class SpiSRAMDown() extends BlackBox with HasBlackBoxInline {
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class SpiSRAMDownIO extends Bundle{
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val addrr = Input(UInt(9.W))
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val addrw = Input(UInt(9.W))
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val dataw = Input( UInt(8.W) )
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val datar = Output( UInt(8.W) )
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val enw = Input(Bool())
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val enr = Input(Bool())
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val clockr = Input(Bool())
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val clockw = Input(Bool())
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}
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val io: SpiSRAMDownIO = IO(new SpiSRAMDownIO)
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setInline("SpiSRAMDown.v",
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"""
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| module SpiSRAMDown(
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| input [7:0] dataw,
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| input [8:0] addrw,
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| input enw,
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| output [7:0] datar,
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| input [8:0] addrr,
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| input enr,
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| input clockr,
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| input clockw
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| );
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| reg [7:0] ram[0:511];
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| reg [7:0] data_r_reg;
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| always @(posedge clockw) begin
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| if(enw) begin
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| ram[addrw] <= #1 dataw;
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| end
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| end
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| always @(posedge clockr) begin
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| if(enr) begin
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| data_r_reg <= #1 ram[addrr];
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| end
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| end
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| assign datar = data_r_reg;
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|endmodule
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""".stripMargin)
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}
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class SpiSRAMUp extends BlackBox with HasBlackBoxInline {
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class SpiSRAMUpIO extends Bundle{
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val addrr = Input(UInt(9.W))
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val addrw = Input(UInt(9.W))
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val dataw = Input( UInt(8.W) )
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val datar = Output( UInt(8.W) )
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val enw = Input(Bool())
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val enr = Input(Bool())
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val clockr = Input(Bool())
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val clockw = Input(Bool())
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}
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val io: SpiSRAMUpIO = IO(new SpiSRAMUpIO)
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setInline("SpiSRAMUp.v",
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"""
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| module SpiSRAMUp(
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| input [7:0] dataw,
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| input [8:0] addrw,
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| input enw,
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| output [7:0] datar,
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| input [8:0] addrr,
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| input enr,
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| input clockr,
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| input clockw
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| );
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| reg [7:0] ram[0:511];
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| reg [7:0] data_r_reg;
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| always @(posedge clockw) begin
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| if(enw) begin
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| ram[addrw] <= #1 dataw;
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| end
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| end
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| always @(posedge clockr) begin
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| if(enr) begin
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| data_r_reg <= #1 ram[addrr];
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| end
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| end
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| assign datar = data_r_reg;
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|endmodule
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""".stripMargin)
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} |