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eb001/src/main/scala/backBoard/ebus/Axis8toN.scala.bk
2024-10-09 17:37:15 +08:00

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package BACK
import chisel3._
import chisel3.util._
class Axis8toNIO_Bundle(dw: Int) extends Bundle{
val enq = Flipped(Decoupled(new AxisNto8IO_Bundle(8)))
val deq = Decoupled(new AxisNto8IO_Bundle(dw))
}
class Axis8toN(dw: Int) extends Module{
require( dw == 16 | dw == 32 | dw == 64 )
assert( io.deq.ready === true.B )
val io: Axis8toNIO_Bundle = IO(new Axis8toNIO_Bundle(dw))
val cnt = RegInit( 0.U( log2Ceil(dw/8).W ) )
val fifo = Reg( new AxisNto8IO_Bundle(dw) )
}