87 lines
1.9 KiB
Scala
87 lines
1.9 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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class BackBoardSlvIO extends Bundle{
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val reset_calib = Input(Bool())
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val oser_pclk = Input(Bool())
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val oser_fclk = Input(Bool())
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val ides_pclk = Input(Bool())
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val ides_fclk = Input(Bool())
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val lvds_down_din = Input(Bool())
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val lvds_down_dout = Output(Bool())
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val lvds_up_din = Input(Bool())
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val lvds_up_dout = Output(Bool())
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}
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abstract class BackBoardSlvBase extends Module{
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val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
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val lvdsSlv = Module(new Lvds_Bus_Slave)
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lvdsSlv.io.rst_n := ~reset.asBool()
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lvdsSlv.io.reset_calib := io.reset_calib
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lvdsSlv.io.oser_pclk := io.oser_pclk
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lvdsSlv.io.oser_fclk := io.oser_fclk
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lvdsSlv.io.ides_pclk := io.ides_pclk
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lvdsSlv.io.ides_fclk := io.ides_fclk
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lvdsSlv.io.lvds_down_din := io.lvds_down_din
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io.lvds_down_dout := lvdsSlv.io.lvds_down_dout
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lvdsSlv.io.lvds_up_din := io.lvds_up_din
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io.lvds_up_dout := lvdsSlv.io.lvds_up_dout
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val downRegTemp = RegInit(VecInit(Seq.fill(32){0.U(8.W)}))
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val downReg = RegInit(VecInit(Seq.fill(32){0.U(8.W)}))
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val upReg = RegInit(VecInit((0 until 32).map{i => i.U(8.W)}))
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}
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trait BackBoardSlvDown{ this: BackBoardSlvBase =>
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val downCnt = Reg(UInt(6.W))
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when( lvdsSlv.io.downstream_rx_data_valid ){
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downRegTemp(downCnt) := lvdsSlv.io.downstream_rx_data_out
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downCnt := downCnt + 1.U
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} .otherwise{
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downCnt := 0.U
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}
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when( lvdsSlv.io.downstream_rx_crc_valid ){
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when( ~lvdsSlv.io.downstream_rx_crc_err ){
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downReg := downRegTemp
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}
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}
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}
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trait BackBoardSlvUp{ this: BackBoardSlvBase =>
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val upCnt = Reg(UInt(6.W))
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lvdsSlv.io.upstream_tx_data_in := upReg(upCnt)
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when( lvdsSlv.io.upstream_tx_data_ready ){
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when( ~RegNext(lvdsSlv.io.upstream_tx_data_ready, false.B) ){
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upCnt := 0.U
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} .otherwise{
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upCnt := upCnt + 1.U
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}
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}
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}
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