196 lines
6.4 KiB
Scala
196 lines
6.4 KiB
Scala
package BACK
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import chisel3._
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import chisel3.util._
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//work in 100MHZ
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class CDRInIO extends Bundle{
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val axis = Decoupled(new AXIS_Bundle(8))
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val serDat = Input(Bool())
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val overCLK = Input(Bool())
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}
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abstract class CDRInBase extends Module{
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def sampleRate: Int = 4
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require( sampleRate == 4 )
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val io: CDRInIO = IO(new CDRInIO)
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}
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trait CDRInOverSample{ this: CDRInBase =>
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val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
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// val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
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// val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
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// val isArbLock = RegInit(false.B)
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// for( i <- 0 until sampleRate ){
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// arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) )
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// when( arbShiftData(i) === "h5A5A5A".U & ~isArbLock ){
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// isArbLock := true.B
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// arbSel := i.U
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// }
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// }
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// when( ( 0 until sampleRate ).map{ i => (arbShiftData(i) === 0.U) }.reduce(_&_) ){
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// isArbLock := false.B
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// }
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// val syncSerDat =
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// Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )
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val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b0001".U(sampleRate.W)) }
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arbCnt := Cat( arbCnt(2,0), arbCnt.extract(3) )
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val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
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when( sampleReg(0) ^ sampleReg(1) ){
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arbLock := arbCnt
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}
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val asyncSerDat = Mux1H(Seq(
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(arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3),
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(arbLock === "b0001".U & arbCnt === "b0010".U) -> sampleReg(0),
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(arbLock === "b0001".U & arbCnt === "b0100".U) -> sampleReg(1),
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(arbLock === "b0001".U & arbCnt === "b1000".U) -> sampleReg(2),
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(arbLock === "b0010".U & arbCnt === "b0001".U) -> sampleReg(2),
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(arbLock === "b0010".U & arbCnt === "b0010".U) -> sampleReg(3),
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(arbLock === "b0010".U & arbCnt === "b0100".U) -> sampleReg(0),
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(arbLock === "b0010".U & arbCnt === "b1000".U) -> sampleReg(1),
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(arbLock === "b0100".U & arbCnt === "b0001".U) -> sampleReg(1),
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(arbLock === "b0100".U & arbCnt === "b0010".U) -> sampleReg(2),
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(arbLock === "b0100".U & arbCnt === "b0100".U) -> sampleReg(3),
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(arbLock === "b0100".U & arbCnt === "b1000".U) -> sampleReg(0),
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(arbLock === "b1000".U & arbCnt === "b0001".U) -> sampleReg(0),
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(arbLock === "b1000".U & arbCnt === "b0010".U) -> sampleReg(1),
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(arbLock === "b1000".U & arbCnt === "b0100".U) -> sampleReg(2),
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(arbLock === "b1000".U & arbCnt === "b1000".U) -> sampleReg(3),
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))
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val syncSerDat = ShiftRegister( asyncSerDat, 2 )
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}
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trait CDRInAxis{ this: CDRInBase =>
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def HeaderByte: Int = 8
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val ETH_PRE = "h55".U(8.W)
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val ETH_SFD = "hD5".U(8.W)
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val STATE_IDLE = 0.U
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val STATE_HEADER = 1.U
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val STATE_PAYLOAD = 2.U
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val STATE_CRC = 3.U
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val stateNext = Wire(UInt(2.W))
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val stateCurr = RegNext( stateNext, STATE_IDLE )
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val crcUnit = Module(new crc32_8)
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val crcOut = crcUnit.io.crc
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val crcCmp = Reg(UInt(32.W))
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val bitCnt = Reg(UInt(4.W))
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val byteCnt = RegInit(0.U(12.W))
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val syncSerDat: Bool
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val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )
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val shiftData = Dualb4b5Decoder(checkSFD(9,0))
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val payloadLen = Reg(UInt(12.W))
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when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
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payloadLen := Cat( shiftData, 0.U(4.W) )
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} .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
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payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
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}
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stateNext :=
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Mux1H(Seq(
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(stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)), STATE_HEADER, STATE_IDLE )), //IDLE
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(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
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(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 9.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD
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(stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 9.U), STATE_IDLE, STATE_CRC )), //CRC
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))
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when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align
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bitCnt := 0.U
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} .otherwise{
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when( bitCnt === 9.U ){
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bitCnt := 0.U
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} .otherwise{
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bitCnt := bitCnt + 1.U
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}
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}
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when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align
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byteCnt := 0.U
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} .elsewhen( bitCnt === 9.U ){
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when( stateCurr === STATE_HEADER ){
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byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
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assert( byteCnt <= (HeaderByte-1).U )
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} .elsewhen( stateCurr === STATE_PAYLOAD ){
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byteCnt := Mux( byteCnt =/= (payloadLen-1.U), byteCnt + 1.U, 0.U )
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assert( byteCnt <= ( payloadLen-1.U ) )
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} .elsewhen( stateCurr === STATE_CRC ){
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byteCnt := Mux( byteCnt =/= 3.U, byteCnt + 1.U, 0.U )
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assert( byteCnt <= 3.U )
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}
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}
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val axis_valid = RegInit(false.B)
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val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) )
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val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )), bitCnt === 9.U )
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val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U, bitCnt === 9.U )
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io.axis.valid := axis_valid
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io.axis.bits.tdata := axis_tdata
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io.axis.bits.tuser := axis_tuser
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io.axis.bits.tlast := axis_tlast
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when( io.axis.fire ){
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axis_valid := false.B
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} .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){
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axis_valid := true.B
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}
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when( stateCurr === STATE_CRC & bitCnt === 9.U ){
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crcCmp := Cat( shiftData, crcCmp(31,8) )
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}
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crcUnit.io.isEnable := ((stateCurr === STATE_HEADER ) | (stateCurr === STATE_PAYLOAD )) & ( bitCnt === 9.U )
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crcUnit.io.dataIn := shiftData
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crcUnit.reset := reset.asBool | ( stateCurr === STATE_IDLE ) //idle
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}
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class CDRIn extends CDRInBase with CDRInOverSample with CDRInAxis
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