module SimTop (

	// output success,
	// output fail,

	input clock, //100MHz
	input reset,
  input clk400


);



wire [3:0] uDatSer;
wire [3:0] dDatSer;




wire [3:0] dmactive;

ExampleRocketSystem s_rocket_mst(
  .clock(clock),
  .reset(reset),
  .resetctrl_hartIsInReset_0(reset),

  .debug_clock(clock),
  .debug_reset(reset),
  .debug_systemjtag_jtag_TCK(1'b0),
  .debug_systemjtag_jtag_TMS(1'b0),
  .debug_systemjtag_jtag_TDI(1'b0),
  .debug_systemjtag_jtag_TDO_data(),
  .debug_systemjtag_jtag_TDO_driven(),
  .debug_systemjtag_reset(reset),
  .debug_systemjtag_mfr_id(11'b0),
  .debug_systemjtag_part_number(16'b0),
  .debug_systemjtag_version(4'b0),
  .debug_ndreset(),
  .debug_dmactive(dmactive[0]),
  .debug_dmactiveAck(dmactive[0]),

  .mmio_apb_0_psel(),
  .mmio_apb_0_penable(),
  .mmio_apb_0_pwrite(),
  .mmio_apb_0_paddr(),
  .mmio_apb_0_pprot(),
  .mmio_apb_0_pwdata(),
  .mmio_apb_0_pstrb(),
  .mmio_apb_0_pready(1'b1),
  .mmio_apb_0_pslverr(1'b0),
  .mmio_apb_0_prdata(32'b0),

  .mmio_ahb_0_hmastlock(),
  .mmio_ahb_0_hsel(),
  .mmio_ahb_0_hready(),
  .mmio_ahb_0_hreadyout(1'b1),
  .mmio_ahb_0_htrans(),
  .mmio_ahb_0_hsize(),
  .mmio_ahb_0_hburst(),
  .mmio_ahb_0_hwrite(),
  .mmio_ahb_0_hprot(),
  .mmio_ahb_0_haddr(),
  .mmio_ahb_0_hwdata(),
  .mmio_ahb_0_hresp(2'b0),
  .mmio_ahb_0_hrdata(32'b0),
  .mmio_ahb_0_hmaster(),
  .mmio_ahb_0_hsplit(16'b0),

  .interrupts(2'b0),

  .cdrio_overCLK(clk400),
  .cdrio_uDatIn(uDatSer[0]),
  .cdrio_uDatOut(),
  .cdrio_dDatIn(1'b0),
  .cdrio_dDatOut(dDatSer[0])
);


ExampleRocketSystem s_rocket_slv0(
  .clock(clock),
  .reset(reset),
  .resetctrl_hartIsInReset_0(reset),

  .debug_clock(clock),
  .debug_reset(reset),
  .debug_systemjtag_jtag_TCK(1'b0),
  .debug_systemjtag_jtag_TMS(1'b0),
  .debug_systemjtag_jtag_TDI(1'b0),
  .debug_systemjtag_jtag_TDO_data(),
  .debug_systemjtag_jtag_TDO_driven(),
  .debug_systemjtag_reset(reset),
  .debug_systemjtag_mfr_id(11'b0),
  .debug_systemjtag_part_number(16'b0),
  .debug_systemjtag_version(4'b0),
  .debug_ndreset(),
  .debug_dmactive(dmactive[1]),
  .debug_dmactiveAck(dmactive[1]),

  .mmio_apb_0_psel(),
  .mmio_apb_0_penable(),
  .mmio_apb_0_pwrite(),
  .mmio_apb_0_paddr(),
  .mmio_apb_0_pprot(),
  .mmio_apb_0_pwdata(),
  .mmio_apb_0_pstrb(),
  .mmio_apb_0_pready(1'b1),
  .mmio_apb_0_pslverr(1'b0),
  .mmio_apb_0_prdata(32'b0),

  .mmio_ahb_0_hmastlock(),
  .mmio_ahb_0_hsel(),
  .mmio_ahb_0_hready(),
  .mmio_ahb_0_hreadyout(1'b1),
  .mmio_ahb_0_htrans(),
  .mmio_ahb_0_hsize(),
  .mmio_ahb_0_hburst(),
  .mmio_ahb_0_hwrite(),
  .mmio_ahb_0_hprot(),
  .mmio_ahb_0_haddr(),
  .mmio_ahb_0_hwdata(),
  .mmio_ahb_0_hresp(2'b0),
  .mmio_ahb_0_hrdata(32'b0),
  .mmio_ahb_0_hmaster(),
  .mmio_ahb_0_hsplit(16'b0),

  .interrupts(2'b0),

  .cdrio_overCLK(clk400),
  .cdrio_uDatIn(uDatSer[1]),
  .cdrio_uDatOut(uDatSer[0]),
  .cdrio_dDatIn(dDatSer[0]),
  .cdrio_dDatOut(dDatSer[1])
);


ExampleRocketSystem s_rocket_slv1(
  .clock(clock),
  .reset(reset),
  .resetctrl_hartIsInReset_0(reset),

  .debug_clock(clock),
  .debug_reset(reset),
  .debug_systemjtag_jtag_TCK(1'b0),
  .debug_systemjtag_jtag_TMS(1'b0),
  .debug_systemjtag_jtag_TDI(1'b0),
  .debug_systemjtag_jtag_TDO_data(),
  .debug_systemjtag_jtag_TDO_driven(),
  .debug_systemjtag_reset(reset),
  .debug_systemjtag_mfr_id(11'b0),
  .debug_systemjtag_part_number(16'b0),
  .debug_systemjtag_version(4'b0),
  .debug_ndreset(),
  .debug_dmactive(dmactive[2]),
  .debug_dmactiveAck(dmactive[2]),

  .mmio_apb_0_psel(),
  .mmio_apb_0_penable(),
  .mmio_apb_0_pwrite(),
  .mmio_apb_0_paddr(),
  .mmio_apb_0_pprot(),
  .mmio_apb_0_pwdata(),
  .mmio_apb_0_pstrb(),
  .mmio_apb_0_pready(1'b1),
  .mmio_apb_0_pslverr(1'b0),
  .mmio_apb_0_prdata(32'b0),

  .mmio_ahb_0_hmastlock(),
  .mmio_ahb_0_hsel(),
  .mmio_ahb_0_hready(),
  .mmio_ahb_0_hreadyout(1'b1),
  .mmio_ahb_0_htrans(),
  .mmio_ahb_0_hsize(),
  .mmio_ahb_0_hburst(),
  .mmio_ahb_0_hwrite(),
  .mmio_ahb_0_hprot(),
  .mmio_ahb_0_haddr(),
  .mmio_ahb_0_hwdata(),
  .mmio_ahb_0_hresp(2'b0),
  .mmio_ahb_0_hrdata(32'b0),
  .mmio_ahb_0_hmaster(),
  .mmio_ahb_0_hsplit(16'b0),

  .interrupts(2'b0),

  .cdrio_overCLK(clk400),
  .cdrio_uDatIn(uDatSer[2]),
  .cdrio_uDatOut(uDatSer[1]),
  .cdrio_dDatIn(dDatSer[1]),
  .cdrio_dDatOut(dDatSer[2])
);


ExampleRocketSystem s_rocket_slv2(
  .clock(clock),
  .reset(reset),
  .resetctrl_hartIsInReset_0(reset),

  .debug_clock(clock),
  .debug_reset(reset),
  .debug_systemjtag_jtag_TCK(1'b0),
  .debug_systemjtag_jtag_TMS(1'b0),
  .debug_systemjtag_jtag_TDI(1'b0),
  .debug_systemjtag_jtag_TDO_data(),
  .debug_systemjtag_jtag_TDO_driven(),
  .debug_systemjtag_reset(reset),
  .debug_systemjtag_mfr_id(11'b0),
  .debug_systemjtag_part_number(16'b0),
  .debug_systemjtag_version(4'b0),
  .debug_ndreset(),
  .debug_dmactive(dmactive[3]),
  .debug_dmactiveAck(dmactive[3]),

  .mmio_apb_0_psel(),
  .mmio_apb_0_penable(),
  .mmio_apb_0_pwrite(),
  .mmio_apb_0_paddr(),
  .mmio_apb_0_pprot(),
  .mmio_apb_0_pwdata(),
  .mmio_apb_0_pstrb(),
  .mmio_apb_0_pready(1'b1),
  .mmio_apb_0_pslverr(1'b0),
  .mmio_apb_0_prdata(32'b0),

  .mmio_ahb_0_hmastlock(),
  .mmio_ahb_0_hsel(),
  .mmio_ahb_0_hready(),
  .mmio_ahb_0_hreadyout(1'b1),
  .mmio_ahb_0_htrans(),
  .mmio_ahb_0_hsize(),
  .mmio_ahb_0_hburst(),
  .mmio_ahb_0_hwrite(),
  .mmio_ahb_0_hprot(),
  .mmio_ahb_0_haddr(),
  .mmio_ahb_0_hwdata(),
  .mmio_ahb_0_hresp(2'b0),
  .mmio_ahb_0_hrdata(32'b0),
  .mmio_ahb_0_hmaster(),
  .mmio_ahb_0_hsplit(16'b0),

  .interrupts(2'b0),

  .cdrio_overCLK(clk400),
  .cdrio_uDatIn(1'b0),
  .cdrio_uDatOut(uDatSer[2]),
  .cdrio_dDatIn(dDatSer[2]),
  .cdrio_dDatOut()
);





// wire debugger_success;

// debuger i_debuger(
//   .success(debugger_success),
// 	.DEBUGER_AWID   (mmio_axi4_0_aw_bits_id),
// 	.DEBUGER_BID    (mmio_axi4_0_b_bits_id),
// 	.DEBUGER_ARID   (mmio_axi4_0_ar_bits_id),
// 	.DEBUGER_RID    (mmio_axi4_0_r_bits_id),

// 	.DEBUGER_AWADDR (mmio_axi4_0_aw_bits_addr),
// 	.DEBUGER_AWVALID(mmio_axi4_0_aw_valid),
// 	.DEBUGER_AWREADY(mmio_axi4_0_aw_ready),

// 	.DEBUGER_WDATA (mmio_axi4_0_w_bits_data),   
// 	.DEBUGER_WSTRB (mmio_axi4_0_w_bits_strb),
// 	.DEBUGER_WVALID(mmio_axi4_0_w_valid),
// 	.DEBUGER_WREADY(mmio_axi4_0_w_ready),

// 	.DEBUGER_BRESP (mmio_axi4_0_b_bits_resp),
// 	.DEBUGER_BVALID(mmio_axi4_0_b_valid),
// 	.DEBUGER_BREADY(mmio_axi4_0_b_ready),

// 	.DEBUGER_ARADDR (mmio_axi4_0_ar_bits_addr),
// 	.DEBUGER_ARVALID(mmio_axi4_0_ar_valid),
// 	.DEBUGER_ARREADY(mmio_axi4_0_ar_ready),

// 	.DEBUGER_RDATA (mmio_axi4_0_r_bits_data),
// 	.DEBUGER_RRESP (mmio_axi4_0_r_bits_resp),
// 	.DEBUGER_RVALID(mmio_axi4_0_r_valid),
// 	.DEBUGER_RREADY(mmio_axi4_0_r_ready),

// 	.CLK(CLK),
// 	.RSTn(RSTn)
	
// );




    
	// reg [1023:0] firmware_file;
	// initial begin
	// 	if ($value$plusargs("%s", firmware_file)) begin
	// 		$display("%s", firmware_file);
	// 		$readmemh(firmware_file, s_rocket.ram.Mem_SRAM.Mem_SRAM_ext.ram);
	// 	end
	// end







// assign success = debugger_success;



initial begin
    s_rocket_mst.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 0;
  s_rocket_slv0.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 1;
  s_rocket_slv1.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 2;
  s_rocket_slv2.tile_prci_domain.tile_reset_domain_tile.core.CoreID = 3;
end

string testName;

`define MEM0 s_rocket_mst.ram.Mem_SRAM.Mem_SRAM_ext.ram
`define MEM1 s_rocket_slv0.ram.Mem_SRAM.Mem_SRAM_ext.ram
`define MEM2 s_rocket_slv1.ram.Mem_SRAM.Mem_SRAM_ext.ram
`define MEM3 s_rocket_slv2.ram.Mem_SRAM.Mem_SRAM_ext.ram

reg [7:0] mem0 [0:200000];
reg [7:0] mem1 [0:200000];
reg [7:0] mem2 [0:200000];
reg [7:0] mem3 [0:200000];

localparam DP = 8192;
integer i;


initial begin

#20

  $readmemh("./tb/sw/build/mstTest.verilog", mem0);
  for ( i = 0; i < DP; i = i + 1 ) begin
    if ( mem0[i*4+0] || mem0[i*4+1] || mem0[i*4+2] || mem0[i*4+3] ) begin
      `MEM0[i] = {mem0[i*4+3], mem0[i*4+2], mem0[i*4+1], mem0[i*4+0]};
    end
    else begin
      `MEM0[i] = 32'h0;
    end

    // $display("MEM0[%d] = %h", i, `MEM0[i]);
	end

  $readmemh("./tb/sw/build/slvTest.verilog", mem1);
  for ( i = 0; i < DP; i = i + 1 ) begin
    if ( mem1[i*4+0] || mem1[i*4+1] || mem1[i*4+2] || mem1[i*4+3] ) begin
      `MEM1[i] = {mem1[i*4+3], mem1[i*4+2], mem1[i*4+1], mem1[i*4+0]};
    end
    else begin
      `MEM1[i] = 32'h0;
    end
	end

  $readmemh("./tb/sw/build/slvTest.verilog", mem2);
  for ( i = 0; i < DP; i = i + 1 ) begin
    if ( mem2[i*4+0] || mem2[i*4+1] || mem2[i*4+2] || mem2[i*4+3] ) begin
      `MEM2[i] = {mem2[i*4+3], mem2[i*4+2], mem2[i*4+1], mem2[i*4+0]};
    end
    else begin
      `MEM2[i] = 32'h0;
    end
	end

  $readmemh("./tb/sw/build/slvTest.verilog", mem3);
  for ( i = 0; i < DP; i = i + 1 ) begin
    if ( mem3[i*4+0] || mem3[i*4+1] || mem3[i*4+2] || mem3[i*4+3] ) begin
      `MEM3[i] = {mem3[i*4+3], mem3[i*4+2], mem3[i*4+1], mem3[i*4+0]};
    end
    else begin
      `MEM3[i] = 32'h0;
    end
  end

end



endmodule