package BACK

import chisel3._
import chisel3.util._


class SlaveRecParserIO extends Module{
  val rec  = Flipped( Decoupled(new AXIS_Bundle(8)) )

  val data = Decoupled(UInt(8.W))

  val stateNext = Output(UInt(4.W))
  val stateCurr = Output(UInt(4.W))

  val frameReq = Valid( new FrameHeader )
  val subMsgReq = Valid( new SubMsgHeader )

  val resp = Input(Bool())
  val isError = Output(Bool())


}

class SlaveRecParser extends Module{
  val io: SlaveRecParserIO = IO(new SlaveRecParserIO)

  val crc = Module(new crc32_8)

  crc.io.isEnable :=
    stateCurr === STATE_HEADER |
    stateCurr === STATE_PAYLOAD_INDEX_STYLE |
    stateCurr === STATE_PAYLOAD_ADDR |
    stateCurr === STATE_PAYLOAD_OP_LENGTH |
    stateCurr === STATE_PAYLOAD_WORKCNT |
    stateCurr === STATE_PAYLOAD_DATA

  crc.io.dataIn := io.rec.bits.tdata

  crc.reset := reset.asBool | stateCurr === STATE_IDLE

  val crcData = Reg(UInt(32.W))
  val isCrcPass = crc.io.crc === Cat( crcData << 8, io.rec.bits.tdata )

  when( stateCurr === STATE_CRC ){
    crcData := Cat( crcData << 8, io.rec.bits.tdata )
  }

  val FRAME_STYLE_COMMON = 0.U
  val FRAME_STYLE_PROBE  = 1.U


  val STATE_IDLE                = 0.U //空闲
  val STATE_HEADER              = 1.U //长度/ /保留2bits //包类型
  val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
  val STATE_PAYLOAD_ADDR        = 3.U //子报文地址
  val STATE_PAYLOAD_OP_LENGTH   = 4.U //子报文命令类型 //子报文长度
  val STATE_PAYLOAD_WORKCNT     = 5.U //子报文工作计数
  val STATE_PAYLOAD_DATA        = 6.U //子报文数据
  val STATE_CRC                 = 7.U //CRC校验
  val STATE_ERROR               = 8.U //
  val STATE_WAIT                = 9.U


  val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext
  val stateCurr = RegNext(stateNext, STATE_IDLE(4.W)); io.stateCurr := stateCurr

  val lengthCnt = Reg(UInt(11.W)) //动态计数器
  val frameLenCnt  = Reg(UInt(12.W)) //帧长度计数



  val isShortRx = ~io.rec.valid //接收长度小于预期




  val frameLenAim  = Reg(UInt(12.W)); io.frameReq.bits.frameLenAim := frameLenAim //帧长度目标
  val frameStyle   = Reg(UInt(2.W));  io.frameReq.bits.frameStyle  := frameStyle  //包类型
  io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_PAYLOAD_INDEX_STYLE)

  val devIndex     = Reg(UInt(14.W)); io.subMsgReq.bits.devIndex := devIndex // 子报文中设备索引
  val style        = Reg(UInt(2.W));  io.subMsgReq.bits.style    := style    // 子报文类型
  val address      = Reg(UInt(16.W)); io.subMsgReq.bits.address  := address  //子报文地址
  val operator     = Reg(UInt(4.W));  io.subMsgReq.bits.operator := operator //子报文命令类型
  val length       = Reg(UInt(12.W)); io.subMsgReq.bits.length   := length   //子报文负载长度
  val workCnt      = Reg(UInt(16.W)); io.subMsgReq.bits.workCnt  := workCnt  //子报文工作计数
  io.subMsgReq.valid := (stateCurr === STATE_PAYLOAD_WORKCNT) & (stateNext === STATE_PAYLOAD_DATA)

  when( stateCurr === STATE_IDLE ){
    lengthCnt := 0.U
  } .elsewhen( stateCurr =/= stateNext ){
    lengthCnt := 0.U
  } .otherwise{
    lengthCnt := lengthCnt + 1.U
  }

  when( stateCurr === STATE_IDLE || stateCurr === STATE_HEADER ){
    frameLenCnt := 0.U
  } .elsewhen( 
    ( stateCurr === STATE_PAYLOAD_INDEX_STYLE ) ||
    ( stateCurr === STATE_PAYLOAD_ADDR        ) ||
    ( stateCurr === STATE_PAYLOAD_OP_LENGTH   ) ||
    ( stateCurr === STATE_PAYLOAD_WORKCNT     ) ||
    ( stateCurr === STATE_PAYLOAD_DATA        )
  ){
    frameLenCnt := frameLenCnt + 1.U
  }

  io.data.valid := stateCurr === STATE_PAYLOAD_DATA
  io.data.bits  := io.rec.bits
  assert( ~(io.data.valid & ~io.data.ready), "Assert Failed! Receive Data was recected by fifo!" )




  when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){
    frameLenAim := io.rec.bits.tdata << 4
  } .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 1.U ){
    frameLenAim := frameLenAim | io.rec.bits.tdata(7,4)
    frameStyle  := io.rec.bits.tdata(1,0)
  }

  when( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 0.U ){
    devIndex := io.rec.bits.tdata << 6
  } .elsewhen( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 1.U ){
    devIndex := devIndex | io.rec.bits.tdata(7,2)
    style    := io.rec.bits.tdata(1,0)
  }

  when( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 0.U ){
    address := io.rec.bits.tdata << 8
  } .elsewhen( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 1.U ){
    address := address | io.rec.bits.tdata
  }

  when( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 0.U ){
    operator := io.rec.bits.tdata(7,4)
    length   := io.rec.bits.tdata(3,0) << 8
  } .elsewhen( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 1.U ){
    length   := length | io.rec.bits.tdata(7,0)
  }

  when( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 0.U ){
    workCnt := io.rec.bits.tdata(7,0) << 8
  } .elsewhen( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 1.U ){
    workCnt := workCnt | io.rec.bits.tdata(7,0)
  }


  stateNext := 
    Mux1H(Seq(
                                                        //必须使用上升沿触发，以避免前一帧长度超过预期
      ( stateCurr === STATE_IDLE                ) -> Mux( ~RegNext(io.rec.valid) & io.rec.axis.valid, STATE_HEADER, STATE_IDLE ), 
      ( stateCurr === STATE_HEADER              ) -> Mux( isShortRx, STATE_ERROR,
          Mux( lengthCnt === 0, STATE_HEADER,
            MuxCase( STATE_ERROR, Array(
              ( io.rec.bits(1,0) === FRAME_STYLE_COMMON ) -> STATE_PAYLOAD_INDEX_STYLE,
              ( io.rec.bits(1,0) === FRAME_STYLE_PROBE  ) -> STATE_CRC,
            ))
          )
        ),
      ( stateCurr === STATE_PAYLOAD_INDEX_STYLE ) -> Mux( isShortRx, STATE_ERROR,
          Mux( lengthCnt === 0, STATE_PAYLOAD_INDEX_STYLE, STATE_PAYLOAD_ADDR )
        ),
      ( stateCurr === STATE_PAYLOAD_ADDR        ) -> Mux( isShortRx, STATE_ERROR,
          Mux( lengthCnt === 0, STATE_PAYLOAD_ADDR, STATE_PAYLOAD_OP_LENGTH )
        ),
      ( stateCurr === STATE_PAYLOAD_OP_LENGTH   ) -> Mux( isShortRx, STATE_ERROR,
          Mux( lengthCnt === 0, STATE_PAYLOAD_OP_LENGTH, STATE_PAYLOAD_WORKCNT )
        ),
      ( stateCurr === STATE_PAYLOAD_WORKCNT     ) -> Mux( isShortRx, STATE_ERROR,
          Mux( lengthCnt === 0.U, STATE_PAYLOAD_WORKCNT, STATE_PAYLOAD_DATA )
        ),
      ( stateCurr === STATE_PAYLOAD_DATA        ) -> Mux( isShortRx, STATE_ERROR,
          Mux( lengthCnt === ( subMsgLen - 1.U), 
            Mux( frameLenCnt === frameLenAim, STATE_CRC, STATE_PAYLOAD_INDEX_STYLE
          ), STATE_PAYLOAD_DATA )
        ),
      ( stateCurr === STATE_CRC                 ) -> 
          Mux( lengthCnt === (4 - 1).U, Mux( isCrcPass, STATE_IDLE, STATE_ERROR), Mux( isShortRx, STATE_ERROR, STATE_CRC ) ),
      ( stateCurr === STATE_ERROR               ) -> Mux( io.resp, STATE_IDLE, STATE_ERROR ), 
      ( stateCurr === STATE_WAIT                ) -> Mux( io.resp, STATE_IDLE, STATE_WAIT  )
    ))



}