[
  {
    "class":"firrtl.EmitAllModulesAnnotation",
    "emitter":"firrtl.VerilogEmitter"
  },
  {
    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
    "targetDir":"generated/"
  },
  {
    "class":"firrtl.transforms.CombinationalPath",
    "sink":"~MIIM|MIIM>io_Busy",
    "sources":[
      "~MIIM|MIIM>io_RStat",
      "~MIIM|MIIM>io_WCtrlData"
    ]
  }
]