package BACK

import chisel3._
import chisel3.util._



class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline {
  class MirrorSRAMDownIO extends Bundle{
      val addrr  = Input(UInt(11.W))
      val addrw  = Input(UInt(10.W))

      val dataw = Input( UInt(16.W) )
      val datar = Output( UInt(8.W) )
      val enw   = Input(Bool())
      val enr   = Input(Bool())

      val clockr = Input(Bool())
      val clockw = Input(Bool())

  }
  val io: MirrorSRAMDownIO = IO(new MirrorSRAMDownIO)

 setInline("MirrorSRAMDown.v",
              """
      | module MirrorSRAMDown(
      |  	input [15:0] dataw,
      |  	input [9:0] addrw,
      |  	input enw,
      |  
      |  	output [7:0] datar,
      |  	input [10:0] addrr,
      |  	input enr,
      |  
      |  	input clockr,
      |   input clockw
      |  );
      |  
      |  	reg [15:0] ram[0:1023];
      |  	reg [7:0] data_r_reg;
      |  
      |  			always @(posedge clockw) begin
      |  				if(enw) begin
      |  					ram[addrw] <= #1 dataw;					
      |  				end
      |       end
      |  
      |       always @(posedge clockr) begin
      |  				if(enr) begin
      |  					data_r_reg <= #1 addrr[0] ? ram[addrr[10:1]][15:8] : ram[addrr[10:1]][7:0];
      |  				end
      |  			end
      |  
      |  	assign datar = data_r_reg;
      |  
      |  initial begin
      |  	for ( integer i = 0; i < 1024; i = i + 1 ) begin
      |  		ram[i] = $random;
      |  	end
      |  
      |  	data_r_reg = $random;
      |  end
      |   
      |endmodule
    """.stripMargin)
}


class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {

  class MirrorSRAMUpIO extends Bundle{
      val addrr  = Input(UInt(10.W))
      val addrw  = Input(UInt(11.W))

      val dataw = Input( UInt(8.W) )
      val datar = Output( UInt(16.W) )
      val enw   = Input(Bool())
      val enr   = Input(Bool())

      val clockr = Input(Bool())
      val clockw = Input(Bool())

  }
  val io: MirrorSRAMUpIO = IO(new MirrorSRAMUpIO)

 setInline("MirrorSRAMUp.v",
              """
      | module MirrorSRAMUp(
      |  	input [7:0]  dataw,
      |  	input [10:0] addrw,
      |  	input enw,
      |  
      |  	output [15:0] datar,
      |  	input [9:0] addrr,
      |  	input enr,
      |  
      |  	input clockr,
      |   input clockw
      |  );
      |  
      |  	reg [7:0] ram[0:2047] /* synthesis syn_ramstyle="block_ram" */;
      |  	reg [15:0] data_r_reg;
      |  
  		|   always @(posedge clockw) begin
  		|     if(enw) begin
      |       ram[addrw] <= #1 dataw;
      |     end
      |   end
      |  
      |   always @(posedge clockr) begin
      |  		if(enr) begin
      |  			data_r_reg <= #1 { ram[2*addrr+1], ram[2*addrr] };
      |  		end
      |  	end
      |  
      |  	assign datar = data_r_reg;
      |  
      |   
      |endmodule
    """.stripMargin)
}



class MirrorSRAMDP extends BlackBox with HasBlackBoxInline {

  class MirrorSRAMDPIO extends Bundle{

      val addrA  = Input(UInt(10.W))
      val datawA  = Input( UInt(16.W) )
      val datarA  = Output( UInt(16.W) )
      val enwA    = Input(Bool())
      val enrA    = Input(Bool())
      val clockA  = Input(Bool())


      val addrB = Input(UInt(10.W))
      val datawB = Input( UInt(16.W) )
      val datarB = Output( UInt(16.W) )
      val enwB   = Input(Bool())
      val enrB   = Input(Bool())
      val clockB = Input(Bool())

  }
  val io: MirrorSRAMDPIO = IO(new MirrorSRAMDPIO)

 setInline("MirrorSRAMDP.v",
              """
      | module MirrorSRAMDP(
      |  	input [15:0]  datawA,
      |  	input [9:0]   addrA,
      |  	input enwA,
      |  	input enrA,
      |  	output [15:0] datarA,
      |  	input clockA,
      |
      |  	input [15:0]  datawB,
      |  	input [9:0]   addrB,
      |  	input enwB,
      |  	input enrB,
      |  	output [15:0] datarB,
      |  	input clockB
      |  );
      |  
      |  reg [15:0] mem[0:1023];
      |  reg [15:0] data_outa_reg = 16'b0;
      |  reg [15:0] data_outb_reg = 16'b0;
      |
      |  assign datarA = data_outa_reg;
      |  assign datarB = data_outb_reg;
      |
      |  always@( posedge clockA ) begin
      |    if( enrA ) begin
      |    end
      |
      |    if( enwA ) begin
      |      mem[addrA] <= datawA;
      |    end else begin
      |      data_outa_reg <= mem[addrA];
      |    end
      |  end
      |
      |
      |  always@( posedge clockB ) begin
      |    if(enrB) begin
      |    end
      |
      |    if( enwB ) begin
      |      mem[addrB] <= datawB;
      |    end else begin
      |      data_outb_reg <= mem[addrB];
      |    end
      |  end
      |
      |
      |  //Gowin_DPB your_instance_name(
      |  //  .douta(datarA), //output [15:0] douta
      |  //  .doutb(datarB), //output [15:0] doutb
      |  //  .clka(clockA), //input clka
      |  //  .ocea(1'b1), //input ocea
      |  //  .cea(1'b1), //input cea
      |  //  .reseta(1'b0), //input reseta
      |  //  .wrea(enwA), //input wrea
      |  //  .clkb(clockB), //input clkb
      |  //  .oceb(1'b1), //input oceb
      |  //  .ceb(1'b1), //input ceb
      |  //  .resetb(1'b0), //input resetb
      |  //  .wreb(enwB), //input wreb
      |  //  .ada(addrA), //input [3:0] ada
      |  //  .dina(datawA), //input [15:0] dina
      |  //  .adb(addrB), //input [3:0] adb
      |  //  .dinb(datawB) //input [15:0] dinb
      |  //);
      |
      |endmodule
    """.stripMargin)
}






class SpiSRAMDown() extends BlackBox with HasBlackBoxInline {
  class SpiSRAMDownIO extends Bundle{
      val addrr  = Input(UInt(9.W))
      val addrw  = Input(UInt(9.W))

      val dataw = Input(  UInt(8.W) )
      val datar = Output( UInt(8.W) )
      val enw   = Input(Bool())
      val enr   = Input(Bool())

      val clockr = Input(Bool())
      val clockw = Input(Bool())

  }
  val io: SpiSRAMDownIO = IO(new SpiSRAMDownIO)

 setInline("SpiSRAMDown.v",
              """
      | module SpiSRAMDown(
      |  	input [7:0] dataw,
      |  	input [8:0] addrw,
      |  	input enw,
      |  
      |  	output [7:0] datar,
      |  	input [8:0] addrr,
      |  	input enr,
      |  
      |  	input clockr,
      |   input clockw
      |  );
      |  
      |  	reg [7:0] ram[0:511];
      |  	reg [7:0] data_r_reg;
      |  
      |  			always @(posedge clockw) begin
      |  				if(enw) begin
      |  					ram[addrw] <= #1 dataw;					
      |  				end
      |       end
      |  
      |       always @(posedge clockr) begin
      |  				if(enr) begin
      |  					data_r_reg <= #1 ram[addrr];
      |  				end
      |  			end
      |  
      |  	assign datar = data_r_reg;
      |  
      |   
      |endmodule
    """.stripMargin)
}


class SpiSRAMUp extends BlackBox with HasBlackBoxInline {

  class SpiSRAMUpIO extends Bundle{
      val addrr  = Input(UInt(9.W))
      val addrw  = Input(UInt(9.W))

      val dataw = Input( UInt(8.W) )
      val datar = Output( UInt(8.W) )
      val enw   = Input(Bool())
      val enr   = Input(Bool())

      val clockr = Input(Bool())
      val clockw = Input(Bool())

  }
  val io: SpiSRAMUpIO = IO(new SpiSRAMUpIO)

 setInline("SpiSRAMUp.v",
              """
      | module SpiSRAMUp(
      |  	input [7:0]  dataw,
      |  	input [8:0] addrw,
      |  	input enw,
      |  
      |  	output [7:0] datar,
      |  	input [8:0] addrr,
      |  	input enr,
      |  
      |  	input clockr,
      |   input clockw
      |  );
      |  
      |  	reg [7:0] ram[0:511];
      |  	reg [7:0] data_r_reg;
      |  
  		|   always @(posedge clockw) begin
  		|     if(enw) begin
      |       ram[addrw] <= #1 dataw;
      |     end
      |   end
      |  
      |   always @(posedge clockr) begin
      |  		if(enr) begin
      |  			data_r_reg <= #1 ram[addrr];
      |  		end
      |  	end
      |  
      |  	assign datar = data_r_reg;
      |  
      |   
      |endmodule
    """.stripMargin)
}