TARGET=riscv64-unknown-elf
RVCC=$(TARGET)-gcc
RVCCVERSION=$(shell $(RVCC) --version | grep ^$(RVCC) | sed 's/^.* //g')
ISR_MARCH=-march=rv32i -mabi=ilp32
APP_MARCH=-march=rv32i -mabi=ilp32
ISR_CFLAGS=-O2
APP_CFLAGS=-O2

SPI_TYPE ?= -spi 0
TRANS_CODE ?= 
DEVCLK ?= --dev1 0 90 --dev2 0 -90
CDRCLK ?= --clk 0 40
CDR_TYPE ?= -cdr 0

ifeq "$(RVCCVERSION)" "12.2.0"
   	ISR_MARCH=-march=rv32izicsr -mabi=ilp32
	APP_MARCH=-march=rv32izicsr -mabi=ilp32
endif

.PHONY: compile tb wave

shin:
	rm -f ./generated/shin/*
	rm -f ./generated/SimCDR/*
	sbt "test:runMain test.testShinModule"

testShin_vl:
	python3 ./tb/shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
	mkdir -p generated/log
	rm -rf generated/log/*
	rm -rf ./tb/build/
	verilator -Wno-fatal  \
	--timescale "1 ns / 1 ps" \
	-y ./generated/shin \
	--trace-fst \
	--binary ./tb/shinTest/ShinTopSpiTb.v \
	--top-module ShinTopSpiTb \
	--Mdir ./tb/build/ \
	+define+IVERILOG_COMPILE \
	--threads 8 \
	-j 0
	./tb/build/VShinTopSpiTb
	python3 ./tb/shinTest/check_testcase.py


testShin:
	python3 ./tb/shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
	mkdir -p generated/log
	rm -rf generated/log/*
	iverilog -Wall  \
	-o ./tb/build/shinTest.iverilog  \
	-y ./generated/shin \
	-I ./generated/shin \
	-D RANDOMIZE_REG_INIT \
	-D IVERILOG_COMPILE \
	./tb/shinTest/ShinTopSpiTb.v 
	vvp  -N ./tb/build/shinTest.iverilog -lxt2 -fst || true
	python3 ./tb/shinTest/check_testcase.py

testShinClk:
	python3 ./tb/shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
	mkdir -p generated/log
	rm -rf generated/log/*
	iverilog -Wall  \
	-o ./tb/build/shinTest_clk.iverilog  \
	-y ./generated/shin \
	-I ./generated/shin \
	-D RANDOMIZE_REG_INIT \
	-D IVERILOG_COMPILE \
	./tb/shinTest/ShinTopSpiTb_clk.v 
	vvp  -N ./tb/build/shinTest_clk.iverilog -lxt2 -fst || true
	python3 ./tb/shinTest/check_testcase.py

testCDR:
	python3 ./tb/shinTest/gen_sim_cdr_clk.py ${CDRCLK}
	iverilog -Wall  \
	-o ./tb/build/simCDR.iverilog  \
	-y ./generated/SimCDR \
	-I ./generated/SimCDR \
	-D RANDOMIZE_REG_INIT \
	-D IVERILOG_COMPILE \
	./tb/shinTest/SimCDRTb.v 
	vvp  -N ./tb/build/simCDR.iverilog -lxt2 -fst


testFilter:
	./tb/shinTest/test_filter.py

vcdFilter:
	gtkwave ./tb/build/test_filter.vcd 1>/dev/null 2>&1 &

fstShin:
	gtkwave ./generated/wave.fst 1>/dev/null 2>&1 &

fstShinClk:
	gtkwave ./generated/wave_clk.fst 1>/dev/null 2>&1 &

ef: 
	sbt "test:runMain test.testModule"

fst:
	gtkwave ./tb/build/wave.fst &

debug_hlm:
	gtkwave -S ./tb/sw/src/view_signal.tcl ./tb/build/wave.fst 1>/dev/null 2>&1 &