package BACK

import chisel3._
import chisel3.util._



class CRC_ERR_Bundle extends Bundle{
  val crc_err       = Bool()
  val crc_err_count = UInt(8.W)
  val cdr_err       = Bool()
}


class Lvds_Bus_SlaveIO extends Bundle{
  val rst_n     = Input(Bool())
  val oser_pclk = Input(Bool())
  val oser_fclk = Input(Bool())
  val ides_pclk = Input(Bool())
  val ides_fclk = Input(Bool())
  

  val lvds_down_din  = Input(Bool())
  val lvds_down_dout = Output(Bool())
  val lvds_up_din    = Input(Bool())
  val lvds_up_dout   = Output(Bool())
    
  val downstream_rx_data_valid = Output(Bool())
  val downstream_rx_data_out   = Output(UInt(8.W))
  val downstream_rx_crc_valid  = Output(Bool())
  val downstream_rx_crc_err = Output(Bool())
  val downstream_rx_crc_err_counter = Output(UInt(8.W))
  val downstream_rx_cdr_err = Output(Bool())
  val downstream_sync = Output(Bool())

  val upstream_tx_data_ready = Output(Bool())
  val upstream_tx_data_in = Input(UInt(8.W))

  val upstream_rx_crc_valid = Output(Bool())
  val upstream_rx_crc_err = Output(Bool())
  val upstream_rx_crc_err_counter = Output(UInt(8.W))
  val upstream_rx_cdr_err = Output(Bool())
}



class Lvds_Bus_Slave extends BlackBox with HasBlackBoxInline {
  val io: Lvds_Bus_SlaveIO = IO(new Lvds_Bus_SlaveIO)

  setInline("lvds_bus_master.v",
              """
  module Lvds_Bus_Slave(
  |  input rst_n,
  |  input oser_pclk,
  |  input oser_fclk,
  |  input ides_pclk,
  |  input ides_fclk,
  |  
  |  input lvds_down_din,
  |  output lvds_down_dout,
  |  input lvds_up_din,
  |  output lvds_up_dout,
  |  
  |  output downstream_rx_data_valid,
  |  output [7:0] downstream_rx_data_out,
  |  output downstream_rx_crc_valid,
  |  output downstream_rx_crc_err,
  |  output [7:0] downstream_rx_crc_err_counter,
  |  output downstream_rx_cdr_err,
  |  output downstream_sync,
  |  output upstream_tx_data_ready,
  |  input [7:0] upstream_tx_data_in,
  |  output upstream_rx_crc_valid,
  |  output upstream_rx_crc_err,
  |  output [7:0] upstream_rx_crc_err_counter,
  |  output upstream_rx_cdr_err
  |);
  |
  |  lvds_bus_slave_top i_lvds_bus_slave(
  |  .rst_n(rst_n),
  |  .oser_pclk(oser_pclk),
  |  .oser_fclk(oser_fclk),
  |  .ides_pclk(ides_pclk),
  |  .ides_fclk(ides_fclk),
  |  
  |  .lvds_down_din(lvds_down_din),
  |  .lvds_down_dout(lvds_down_dout),
  |  .lvds_up_din(lvds_up_din),
  |  .lvds_up_dout(lvds_up_dout),
  |  
  |  .downstream_rx_data_valid(downstream_rx_data_valid), 
  |  .downstream_rx_data_out(downstream_rx_data_out),
  |  .downstream_rx_crc_valid(downstream_rx_crc_valid),
  |  .downstream_rx_crc_err(downstream_rx_crc_err),
  |  .downstream_rx_crc_err_counter(downstream_rx_crc_err_counter),
  |  .downstream_rx_cdr_err(downstream_rx_cdr_err),
  |  .downstream_sync(downstream_sync),
  |  .upstream_tx_data_ready(upstream_tx_data_ready),
  |  .upstream_tx_data_in(upstream_tx_data_in),
  |  .upstream_rx_crc_valid(upstream_rx_crc_valid),
  |  .upstream_rx_crc_err(upstream_rx_crc_err),
  |  .upstream_rx_crc_err_counter(upstream_rx_crc_err_counter),
  |  .upstream_rx_cdr_err(upstream_rx_cdr_err)
  |  );
  |endmodule
    """.stripMargin)
}