package BACK

import chisel3._
import chisel3.util._


class CDR_Master_Interface_Bundle extends CDRData{
  val op       = UInt(2.W)
}

class SpiSlvIO extends Bundle{
  val CS   = Input(Bool())
  val MISO = Output(Bool())
  val MOSI = Input(Bool())

  val CDRIn  = Flipped(Decoupled(new CDRData))
  val CDROut = Decoupled(new CDRData)

  val interrupt = Output(Bool())


}

class SpiSlv extends Module with RequireAsyncReset{
  val io: SpiSlvIO = IO(new SpiSlvIO)

  // val spiTrans  = Reg( new CDR_Master_Interface_Bundle )
  val centReg = RegInit(0.U.asTypeOf(new CDR_Master_Interface_Bundle))

  io.CDRIn.ready := io.CS
  io.interrupt   := false.B
  io.MISO := RegNext(centReg.asUInt.extract( 6+8+32+2+16-1 ))

  when( ~io.CS ){
    
    centReg := Cat(centReg.asUInt( 6+8+32+2+16-2, 0 ), io.MOSI).asTypeOf(new CDR_Master_Interface_Bundle)
  } .otherwise{

    when( io.CDROut.fire ){
      centReg.op := OPBUSY
    }
    when( io.CDRIn.valid ){
      when( centReg.op === OPBUSY & centReg.address === io.CDRIn.bits.address ){
        centReg.address  := io.CDRIn.bits.address
        centReg.register := io.CDRIn.bits.register
        centReg.data     := io.CDRIn.bits.data
        centReg.hash     := 0.U
        centReg.op       := OPIDLE        
      } .otherwise{
        io.interrupt := true.B
      }

    }

  }

  val CDROutValid = RegInit(false.B); io.CDROut.valid := CDROutValid
  val CDROutInfo  = Reg(new CDRData); io.CDROut.bits  := CDROutInfo

  when( io.CDROut.fire ){
    CDROutValid := false.B
  } .elsewhen( io.CS & centReg.op === OPMSTT & ~CDROutValid ){
    CDROutValid := true.B



    CDROutInfo.address  := centReg.address
    CDROutInfo.register := centReg.register
    CDROutInfo.data     := centReg.data
    CDROutInfo.hash     := 0.U
  }




  def OPIDLE = 0.U
  def OPMSTT = 1.U
  // def OPSLVT = 2.U
  def OPBUSY = 3.U



}